公开(公告)号：US20250167093A1

公开(公告)日：2025-05-22

申请号：US18794303

申请日：2024-08-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： DOHOON KIM

IPC: H01L23/498 ,  H01L23/00

Abstract: A semiconductor package includes: a package substrate including an insulating layer and a plurality of conductive patterns within the insulating layer and respectively including a wiring portion and a via portion; a semiconductor chip on the package substrate and connected to the plurality of conductive patterns; and a molding member that covers the package substrate and the semiconductor chip. The semiconductor chip is closer to a second edge than to an opposite first edge of the package substrate, the plurality of conductive patterns includes a first conductive pattern overlapping a first side surface of the semiconductor chip in a vertical direction and a second conductive pattern overlapping a second side surface of the semiconductor chip in a vertical direction, and a thickness in the vertical direction of a wiring portion of the first conductive pattern is different from a thickness of a wiring portion of the second conductive pattern.