公开(公告)号：US20240431026A1

公开(公告)日：2024-12-26

申请号：US18749099

申请日：2024-06-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaeho CHOI ,  Jonghoon KIM ,  Dongyoon SEO ,  Dohyung KIM ,  Wonseop LEE ,  Daae HUH

IPC: H05K1/11 ,  H05K1/18

Abstract: An apparatus including via structures capable of reducing crosstalk effects is provided. The apparatus includes a printed circuit board (PCB) including sequentially stacked multi-layers, a first via structure that partially penetrates the multilayers of the PCB and is connected to a first metal plate on a first layer of the multilayers, and a second via structure adjacent to the first via structure in a horizontal direction, partially penetrating the multi-layers of the PCB, and connected to a second metal plate disposed on a second layer of the multi-layers. A portion where the first metal plate and the second metal plate overlap each other is configured to provide a first mutual capacitive coupling between the first and second via structures.

公开(公告)号：US20230066242A1

公开(公告)日：2023-03-02

申请号：US17707267

申请日：2022-03-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Daae HUH ,  Dongyeop KIM

IPC: H01L23/522

Abstract: A substrate for semiconductor module includes a plurality of insulating layers sequentially stacked on one another, N signal lines transmitting N signals respectively, the N signal lines having N vias that at least partially penetrate through the plurality of insulating layers and are arranged in an N-sided polygon shape in a plan view, and a capacitor element configured to provide capacitive coupling between the N signal lines, the capacitor element having a first coupling element that provides capacitive coupling between first and second vias adjacent to each other among the N vias and a second coupling element that provides capacitive coupling between third and fourth vias that are not adjacent to each other among the N vias.