公开(公告)号：US20150162331A1

公开(公告)日：2015-06-11

申请号：US14326471

申请日：2014-07-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dae-Lim KANG ,  Min-Ho KWON ,  Wei-Hua HSU ,  Sang-Hyun WOO ,  Hwa-Sung RHEE ,  Jun-Suk CHOI

IPC: H01L27/088 ,  H01L21/66

CPC classification number: H01L22/34 ,  H01L27/0886

Abstract: A test pattern of a semiconductor device is provided, which includes first and second fins formed to project from a substrate and arranged to be spaced apart from each other, first and second gate structures formed to cross the first and second fins, respectively, a first source region and a first drain region arranged on the first fin on one side and the other side of the first gate structure, a second source region and a second drain region arranged on the second fin on one side and the other side of the second gate structure, a first conductive pattern connected to the first and second drain regions to apply a first voltage to the first and second drain regions and a second conductive pattern connecting the first source region and the second gate structure to each other.

Abstract translation: 提供了一种半导体器件的测试图案，其包括形成为从衬底突出并布置成彼此间隔开的第一和第二鳍片，分别形成为跨越第一和第二鳍片的第一和第二栅极结构，第一和第二鳍片 源极区域和布置在第一鳍片的第一栅极结构的一侧和另一侧上的第一漏极区域，在第二栅极的一侧和另一侧上布置在第二鳍片上的第二源极区域和第二漏极区域 结构，连接到第一和第二漏极区域以将第一电压施加到第一和第二漏极区域的第一导电图案以及将第一源极区域和第二栅极结构彼此连接的第二导电图案。

公开(公告)号：US20170062420A1

公开(公告)日：2017-03-02

申请号：US15222300

申请日：2016-07-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jung-Gun YOU ,  Dae-Lim KANG ,  Myung-Yoon UM ,  Jeong-Hyo LEE ,  Jae-Yup CHUNG ,  Jun-Sun HWANG ,  Bo-Cheol JEONG

IPC: H01L27/088 ,  H01L29/40 ,  H01L29/423

CPC classification number: H01L27/0886 ,  H01L21/823481 ,  H01L29/0847 ,  H01L29/408 ,  H01L29/42376 ,  H01L29/4238

Abstract: A semiconductor device including a first fin pattern and a second fin pattern which have respective short sides facing each other and are separated from each other, a first field insulating layer which is around the first fin pattern and the second fin pattern, a second field insulating layer and a third field insulating layer which are between the first fin pattern and the second fin pattern, a first gate which is formed on the first fin pattern to intersect the first fin pattern, a second gate which is formed on the second field insulating layer, and a third gate which is formed on the third field insulating layer, wherein upper surfaces of the second and third field insulating layers protrude further upward than an upper surface of the first field insulating layer, and a distance between the first gate and the second gate is equal to a distance between the second gate and the third gate.

Abstract translation: 一种半导体器件，包括：第一鳍状图案和第二鳍状图案，其具有彼此相对的彼此分离的短边;第一场绝缘层，其围绕第一鳍状图案和第二鳍状图案;第二场隔绝 层和第三场绝缘层，位于第一鳍状图案和第二鳍状图案之间，形成在第一鳍状图案上以与第一鳍状图案相交的第一栅极，形成在第二场绝缘层上的第二栅极 以及形成在第三场绝缘层上的第三栅极，其中第二和第三场绝缘层的上表面比第一场绝缘层的上表面进一步向上突出，并且第一栅极和第二栅极之间的距离 栅极等于第二栅极和第三栅极之间的距离。