公开(公告)号：US20160133314A1

公开(公告)日：2016-05-12

申请号：US14793749

申请日：2015-07-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Doo-Hee HWANG ,  Sang-Kyu KANG ,  Dong-Yang LEE ,  Jae-Yeon CHOI ,  Jong-Hyun CHOI

IPC: G11C11/406

CPC classification number: G11C11/40611 ,  G11C7/1063 ,  G11C11/406

Abstract: A semiconductor memory device includes a memory cell array and a refresh control circuit. The memory cell array includes a plurality of memory cell rows. The refresh control circuit performs a normal refresh operation on the plurality of memory cell rows and performs a weak refresh operation on a plurality of weak pages of the plurality of memory cell rows. Each of the weak pages includes at least one weak cell whose data retention time is smaller than normal cells. The refresh control circuit transmits a refresh flag signal to a memory controller external to the semiconductor memory device when the refresh control circuit performs the weak refresh operation on the weak pages in a normal access mode.

Abstract translation: 半导体存储器件包括存储单元阵列和刷新控制电路。 存储单元阵列包括多个存储单元行。 刷新控制电路对多个存储单元行执行正常刷新操作，并对多个存储单元行的多个弱页执行弱刷新操作。 每个弱页包括至少一个数据保留时间小于正常单元的弱单元。 当刷新控制电路在正常访问模式下对弱页执行弱刷新操作时，刷新控制电路将刷新标志信号发送到半导体存储器件外部的存储器控​​制器。