公开(公告)号：US20240303153A1

公开(公告)日：2024-09-12

申请号：US18472682

申请日：2023-09-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jeong Hoan PARK ,  Yeon Soo KWON ,  Hancheon YUN ,  Jungyu LEE ,  Jaeseung JEONG

IPC: G06F11/07

CPC classification number: G06F11/0793

Abstract: An error correction circuit includes a clock delay circuit configured to receive an input clock, delay the input clock by a desired time period to generate a delayed clock, and output one of the input clock and the delayed clock as an output clock in response to a select signal, an error detection circuit configured to, receive the output clock and input data, generate output data and latch data based on the output clock and the input data, and detect a margin error based on the output data and the latch data, and a control circuit configured to correct the detected margin error, the correcting the margin error including adjusting a level of the select signal based on whether the margin error has been detected.