公开(公告)号：US20240315008A1

公开(公告)日：2024-09-19

申请号：US18383201

申请日：2023-10-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： JUN-BUM LEE ,  JUNSOO KIM ,  JAE HYUN CHOI ,  DONGSIK KONG ,  JIHYE KWON ,  TAEYOON AN ,  Hyun Seung CHOI

IPC: H10B12/00

CPC classification number: H10B12/34 ,  H10B12/053 ,  H10B12/315

Abstract: A semiconductor memory device is provided. The semiconductor device may include a semiconductor substrate having a device isolation trench defining active regions, a device isolation layer disposed in the device isolation trench, gate trenches extending in a first direction and crossing the active regions of the semiconductor substrate and the device isolation layer, word lines disposed in the gate trenches, respectively, each of the gate trenches may include first trench sections in the active regions and second trench sections in the device isolation layer, the first trench sections may have a first depth, and the second trench section may have a second depth greater than the first depth, the device isolation layer may include a lower portion positioned at a level lower than bottom surfaces of the first trench sections and an upper portion on the lower portion, and the lower portion may be formed of a dielectric material having a lower dielectric constant than that of the upper portion.

公开(公告)号：US20240377988A1

公开(公告)日：2024-11-14

申请号：US18535027

申请日：2023-12-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： SOOYONG LEE ,  JAE HYUN CHOI

IPC: G06F3/06

Abstract: A memory device may include a memory cell array including first to fourth memory cells respectively connected to first to fourth word lines, a sense amplifier including a first sensing circuit that is configured to generate a first weighted sum based on a first weight stored in the first memory cell and a second weight stored in the third memory cell, in response to an activation of the first and third word lines at a first time point, an input and output circuit that is configured to output the first weighted sum to an external device in response to a first read command, and a restore circuit that is configured to perform a restore operation for storing a first data item stored in the second memory cell to the first memory cell and for storing a second data item stored in the fourth memory cell to the third memory cell after the first time point.