公开(公告)号：US20220262944A1

公开(公告)日：2022-08-18

申请号：US17734686

申请日：2022-05-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JINWOO JEONG ,  JAEHYOUNG LIM

IPC: H01L29/78 ,  H01L21/8234 ,  H01L21/8238 ,  H01L29/66 ,  H01L27/092 ,  H01L27/12 ,  H01L29/06

Abstract: A semiconductor device includes a substrate that includes a first active region and a second active region, a device isolation layer between the first active region and the second active region, a gate structure that extends in a first direction and runs across the first active region and the second active region, a first active contact pattern on the first active region on one side of the gate structure, a second active contact pattern on the second active region on another side of the gate structure, and a connection pattern that is on the device isolation layer and connects the first active contact pattern and the second active contact pattern to each other. The connection pattern extends in a second direction and runs across the gate structure. Portions of the first active contact pattern and the second active contact pattern extend in the first direction and overlap the device isolation layer.

公开(公告)号：US20210028304A1

公开(公告)日：2021-01-28

申请号：US16781991

申请日：2020-02-04

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JINWOO JEONG ,  JAEHYOUNG LIM

IPC: H01L29/78 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/092 ,  H01L27/12 ,  H01L29/06 ,  H01L29/66

Abstract: A semiconductor device includes a substrate that includes a first active region and a second active region, a device isolation layer between the first active region and the second active region, a gate structure that extends in a first direction and runs across the first active region and the second active region, a first active contact pattern on the first active region on one side of the gate structure, a second active contact pattern on the second active region on another side of the gate structure, and a connection pattern that is on the device isolation layer and connects the first active contact pattern and the second active contact pattern to each other. The connection pattern extends in a second direction and runs across the gate structure. Portions of the first active contact pattern and the second active contact pattern extend in the first direction and overlap the device isolation layer.

公开(公告)号：US20210165946A1

公开(公告)日：2021-06-03

申请号：US17034634

申请日：2020-09-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： JUNGKYU CHAE ,  JINWOO JEONG ,  KWANYOUNG CHUN

IPC: G06F30/392 ,  G06F30/3312

Abstract: A method of manufacturing an integrated circuit includes: generating layout data of the integrated circuit by placing and routing standard cells that define the integrated circuit, the standard cells including a nanosheet; generating timing analysis data by performing a timing analysis of the integrated circuit using the layout data; and regenerating the layout data of the integrated circuit by replacing and rerouting the standard cells that define the integrated circuit based on the timing analysis data and a shape of the nanosheet of the placed standard cells.