公开(公告)号：US12282317B2

公开(公告)日：2025-04-22

申请号：US17680958

申请日：2022-02-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sung Hee Lee ,  Jae Yoon Kim ,  Jung Hwan Moon ,  Jung Hoon Bak ,  Kyu-Baik Chang ,  Jae Hoon Jeong ,  Min Kyoung Joo

IPC: G05B19/418 ,  G06N5/02

Abstract: A wafer defect test apparatus in which a defect prediction performance is improved and a simulation time is shortened is provided. The wafer defect test apparatus comprises a wafer variable generator which receives a first structural measurement data and a first process condition data of a first wafer, and a second structural measurement data and a second process condition data of a second wafer, generates a first process variable and a second process variable based on the first structural measurement data and the first process condition data, and generates a third process variable and a fourth process variable based on the second structural measurement data and the second process condition data, an abnormal wafer index generating circuit which generates a first wafer vector of the first process variable and second process variable, generates a second wafer vector of the third process variable and fourth process variable, calculates a first Euclidean distance between the first wafer vector and the second wafer vector, calculates a first Cosine distance between the first wafer vector and the second wafer vector, and generates a first abnormal wafer index of the first wafer based on a product of the first Euclidean distance and the first Cosine distance, and a prediction model generating circuit which receives a first characteristic variable which is a test result of the first wafer, and generates a wafer defect prediction model through a regression based on the first process variable, the second process variable, the first characteristic variable, and the first abnormal wafer index.

公开(公告)号：US10978048B2

公开(公告)日：2021-04-13

申请号：US15987115

申请日：2018-05-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Tae Jin Lee ,  Young Woo Lee ,  Seok Yeong Jung ,  Chakladar Subhojit ,  Jae Hoon Jeong ,  Jun Hui Kim ,  Jae Geun Lee ,  Hyun Woong Lim ,  Soo Min Kang ,  Eun Hye Shin ,  Seong Min Je

IPC: G10L17/00 ,  G10L15/08 ,  G10L15/22 ,  G10L15/28 ,  G10L15/26 ,  G10L15/30 ,  G10L25/78 ,  G10L15/34

Abstract: An apparatus comprising one or more processors, a communication circuit, and a memory for storing instructions, which when executed, performs a method of recognizing a user utterance. The method comprises: receiving first data associated with a user utterance, performing, a first determination to determine whether the user utterance includes the first data and a specified word, performing a second determination to determine whether the first data includes the specified word, transmitting the first data to an external server, receiving a text generated from the first data by the external server, performing a third determination to determine whether the received text matches the specified word, and determining whether to activate the voice-based input system based on the third determination.

公开(公告)号：US09471162B2

公开(公告)日：2016-10-18

申请号：US14508251

申请日：2014-10-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kee Sung Bae ,  Sang Bae Park ,  Sang Hoon Lee ,  Jae Hoon Jeong ,  Kyung Sun Cho ,  Seong Seol Hong ,  Dong Jin Lee ,  Mi Jin Choi

IPC: G06F3/041 ,  G06F1/16

CPC classification number: G06F3/041 ,  G06F1/1652 ,  G06F2203/04102

Abstract: A display apparatus and method are provided. The display apparatus includes a display including a plurality of independent display elements (IDEs) configured for shape deformation, and a controller configured to determine whether the display is deformed by transmitting a plurality of signals to the plurality of IDEs and receiving signals output from the plurality of IDEs in response to the transmitted signals.

Abstract translation: 提供了一种显示装置和方法。 显示装置包括显示器，其包括被配置为形状变形的多个独立显示元件（IDE），以及控制器，被配置为通过向多个IDE发送多个信号以及从多个输出端发送多个信号来确定显示是否变形 的响应于所发送的信号的IDE。