公开(公告)号：US20130215307A1

公开(公告)日：2013-08-22

申请号：US13771409

申请日：2013-02-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yu Jin PARK ,  Ji Min CHEON ,  Jin Ho SEO ,  Ji Hun SHIN ,  Seog Heon HAM

IPC: H03K5/1252 ,  H04N5/378

CPC classification number: H03K5/1252 ,  H04N5/378

Abstract: A correlated double sampling (CDS) circuit includes a correction circuit configured to receive an input pixel signal through a first node via a column line, correct the input pixel signal, and output the corrected pixel signal through a second node; and a comparator including first and second input terminals, the first input terminal being connected to the second node and being configured to receive the corrected pixel signal, and the second input terminal configured to receive a ramp signal, the comparator being configured to compare the corrected pixel signal with the ramp signal and output a comparison signal indicating a result of the comparing, wherein the correction circuit includes, a first capacitor connected between the first and second nodes, and one or more metal lines disposed adjacent to the first capacitor, and wherein at least one other capacitor is formed by the first capacitor and the metal line.

Abstract translation: 相关双采样（CDS）电路包括校正电路，配置为经由列线接收通过第一节点的输入像素信号，校正输入像素信号，并通过第二节点输出经校正的像素信号; 以及比较器，包括第一和第二输入端子，所述第一输入端子连接到所述第二节点并且被配置为接收所述校正的像素信号，并且所述第二输入端子被配置为接收斜坡信号，所述比较器被配置为将所述校正的 并且输出表示比较结果的比较信号，其中所述校正电路包括连接在所述第一和第二节点之间的第一电容器和与所述第一电容器相邻布置的一个或多个金属线，并且其中 至少一个其它电容器由第一电容器和金属线形成。