公开(公告)号：US12231152B2

公开(公告)日：2025-02-18

申请号：US18096557

申请日：2023-01-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jong Hoon Shin ,  Ardavan Pedram ,  Joseph Hassoun

IPC: H03M7/30 ,  G06F15/78 ,  G06N3/0495 ,  G06N3/063 ,  H03M7/42 ,  H03M7/46

Abstract: A runtime bit-plane data-format optimizer for a processing element includes a sparsity-detector and a compression-converter. The sparsity-detector selects a bit-plane compression-conversion format during a runtime of the processing element using a performance model that is based on a first sparsity pattern of first bit-plane data stored in a memory exterior to the processing element and a second sparsity pattern of second bit-plane data that is to be stored in a memory within the processing element. The second sparsity pattern is based on a runtime configuration of the processing element. The first bit-plane data is stored using a first bit-plane compression format and the bit-plane second data is to be stored using a second bit-plane compression format. The compression-conversion circuit converts the first bit-plane compression format of the first data to be the second bit-plane compression format of the second data.

公开(公告)号：US20210357748A1

公开(公告)日：2021-11-18

申请号：US16990970

申请日：2020-08-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jong Hoon Shin ,  Ali Shafiee Ardestani ,  Hamzah Ahmed Ali Abdelaziz ,  Joseph H. Hassoun

IPC: G06N3/08 ,  G06F17/16

Abstract: A system and method for weight preprocessing. In some embodiments, the method includes performing intra-tile preprocessing of a first weight tensor to form a first pre-processed weight tensor, and performing inter-tile preprocessing of the first pre-processed weight tensor, to form a second pre-processed weight tensor. The intra-tile preprocessing may include moving a first element of a first weight tile of the first weight tensor by one position, within the first weight tile, in a lookahead direction or in a lookaside direction. The inter-tile preprocessing may include moving a first row of a weight tile of the first pre-processed weight tensor by one position in a lookahead direction or by one position in a lookaside direction.

公开(公告)号：US11874928B2

公开(公告)日：2024-01-16

申请号：US17000748

申请日：2020-08-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ki Seok Bae ,  Jong Hoon Shin ,  Ki Tak Kim ,  Hye Soo Lee ,  Jin Su Hyun ,  Hyo Sun Hwang

IPC: G06F21/57 ,  H04L9/08 ,  H04L9/32

CPC classification number: G06F21/575 ,  G06F21/572 ,  H04L9/0861 ,  H04L9/0897 ,  H04L9/3242 ,  H04L9/3247 ,  H04L9/3268 ,  G06F2221/033

Abstract: Provided is a security device, an electronic device, a secure boot management system, a method for generating a boot image and a method for executing a boot chain. The security device includes a key deriver configured to receive a root key and a protected boot key included in a boot image and generate a derived key according to a key protection method using the root key and the protected boot key, a key processor configured to perform verification according to the key protection method using the generated derived key to extract a boot key from the protected boot key included in the boot image, a secure booter configured to perform verification on a protected execution image included in the boot image using the extracted boot key, and a processor configured to execute a verified execution image on which the verification has been completed by the secure booter.

公开(公告)号：US20210240833A1

公开(公告)日：2021-08-05

申请号：US17000748

申请日：2020-08-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ki Seok BAE ,  Jong Hoon Shin ,  Ki Tak Kim ,  Hye Soo Lee ,  Jin Su Hyun ,  Hyo Sun Hwang

IPC: G06F21/57 ,  H04L9/08 ,  H04L9/32

Abstract: Provided is a security device, an electronic device, a secure boot management system, a method for generating a boot image and a method for executing a boot chain. The security device includes a key deriver configured to receive a root key and a protected boot key included in a boot image and generate a derived key according to a key protection method using the root key and the protected boot key, a key processor configured to perform verification according to the key protection method using the generated derived key to extract a boot key from the protected boot key included in the boot image, a secure booter configured to perform verification on a protected execution image included in the boot image using the extracted boot key, and a processor configured to execute a verified execution image on which the verification has been completed by the secure booter.

公开(公告)号：US12224774B2

公开(公告)日：2025-02-11

申请号：US18096551

申请日：2023-01-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jong Hoon Shin ,  Ardavan Pedram ,  Joseph Hassoun

IPC: H03M7/30 ,  G06F8/41 ,  G06N3/0495 ,  G06N3/063 ,  H03M7/46

Abstract: A runtime data-format optimizer for a processing element includes a sparsity-detector and a compression-converter. The sparsity-detector selects a first compression-conversion format during a runtime of the processing element based on a performance model that is based on a first sparsity pattern of first data stored in a first memory that is exterior to the processing element and a second sparsity pattern of second data that is to be stored in a second memory within the processing element. The second sparsity pattern is based on a runtime configuration of the processing element. The first data is stored in the first memory using a first compression format and the second data is to be stored in the second memory using a second compression format. The compression-conversion circuit converts the first compression format of the first data to be the second compression format of the second data based on the first compression-conversion format.