公开(公告)号：US20230060946A1

公开(公告)日：2023-03-02

申请号：US17871902

申请日：2022-07-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seungsoo Ha ,  Juyoun Choi ,  Junho Lee

IPC: H01L23/498 ,  H01L23/31

Abstract: The upper redistribution structure of the semiconductor package includes an upper redistribution insulating layer disposed on a semiconductor chip; a first upper redistribution line pattern extending in a horizontal direction inside the upper redistribution insulating layer; a first upper redistribution via pattern extending in a vertical direction inside the upper redistribution insulating layer and configured to connect plurality of first conductive pads to the first upper redistribution line pattern; a pad line pattern extending in the horizontal direction in an upper portion of the upper redistribution insulating layer and configured to connect plurality of second conductive pads with each other; and a pad via pattern extending in the vertical direction inside the upper redistribution insulating layer and configured to connect at least one of the plurality of first conductive pads to the conductive connection member.

公开(公告)号：US12255160B2

公开(公告)日：2025-03-18

申请号：US17742862

申请日：2022-05-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Juyoun Choi ,  Eunjung Lee ,  Junho Lee ,  Seungsoo Ha

IPC: H01L23/538 ,  H01L23/00 ,  H01L23/498 ,  H01L23/64 ,  H01L23/66 ,  H01L25/10

Abstract: Provided is a semiconductor package including a pair of differential signal wiring lines including a first differential signal wiring line and a second differential signal wiring line, extending parallel to and spaced apart from each other, a lower equal potential plate in a lower wiring layer under the signal wiring layer, an upper equal potential plate in an upper wiring layer above the signal wiring layer, and a wiring insulating layer adjacent to the pair of differential signal wiring lines, the lower equal potential plate, and the upper equal potential plate, the wiring insulating layer filling spaces between the signal wiring layer, the lower wiring layer, and the upper wiring layer, at least one of the lower equal potential plate and the upper equal potential plate including an impedance opening overlapping the pair of differential signal wiring lines in a vertical direction and is filled by the wiring insulating layer.