公开(公告)号：US20210311896A1

公开(公告)日：2021-10-07

申请号：US17347769

申请日：2021-06-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jiwoong KIM ,  Dongjoo KIM ,  Jaekuk PARK ,  Yujin OH ,  Moonki JANG ,  Jieun JEONG

IPC: G06F13/38 ,  B60R16/023 ,  B60T7/12 ,  G06F11/14 ,  H04L12/40 ,  G06F11/07 ,  G06F13/40

Abstract: A system-on-chip (SoC) includes a processor, a system interconnect (a first bus) connected to the processor, a physical layer protocol (PHY) intellectual property (IP) block, a second bus connected to the processor, and a reset controller connected to the first bus and the second bus. The processor includes a plurality of central processing unit (CPU) cores. The PHY IP block, connected to the first bus, includes a plurality of PHY IPs including physical layers and is connected to external devices. The reset controller detects an abnormal state of the processor based on a signal from the processor, or an absence of a signal from the processor. The reset controller applies a reset signal to the PHY IP block in response to the detected abnormal state. The PHY IP block outputs a corresponding preset data to respective one of the external devices in response to the reset signal during a reset period.

公开(公告)号：US20220283888A1

公开(公告)日：2022-09-08

申请号：US17752008

申请日：2022-05-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jiwoong KIM ,  Moonki JANG

IPC: G06F11/07

Abstract: A system-on-chip is provided. The system-on-chip includes a system bus, a plurality of IP units connected to the system bus, a processor unit including a plurality of cores configured to control the plurality of IP units via the system bus, a monitoring unit configured to monitor a state of the processor unit, and an error detection unit configured to operate as a master device for the plurality of IP units and monitor a register in which error information indicating whether an error has occurred in each of the plurality of IP units is stored.