公开(公告)号：US11055221B2

公开(公告)日：2021-07-06

申请号：US16424452

申请日：2019-05-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Vikas Sinha ,  Hien Le ,  Tarun Nakra ,  Yingying Tian ,  Apurva Patel ,  Omar Torres

IPC: G06F12/08 ,  G06F12/0831 ,  G06F11/07 ,  G06F12/0868

Abstract: According to one general aspect, an apparatus may include a processor configured to issue a first request for a piece of data from a cache memory and a second request for the piece of data from a system memory. The apparatus may include the cache memory configured to temporarily store a subset of data. The apparatus may include a memory interconnect. The a memory interconnect may be configured to receive the second request for the piece of data from the system memory. The a memory interconnect may be configured to determine if the piece of memory is stored in the cache memory. The a memory interconnect may be configured to, if the piece of memory is determined to be stored in the cache memory, cancel the second request for the piece of data from the system memory.