公开(公告)号：US20220139879A1

公开(公告)日：2022-05-05

申请号：US17325907

申请日：2021-05-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： WANSOO PARK ,  SANG SUB SONG ,  KYUNG SUK OH

IPC: H01L25/065

Abstract: Disclosed is a semiconductor package comprising a substrate, a chip stack including semiconductor chips stacked in an ascending stepwise shape on the substrate, first power/ground wires through which the substrate is connected to a lowermost semiconductor chip of the chip stack and neighboring semiconductor chips of the chip stack are connected to each other, and a second power/ground wire that extends from a first semiconductor chip and is connected to the substrate. The first semiconductor chip is one semiconductor chip other than the lowermost semiconductor chip and an uppermost semiconductor chip of the chip stack. The chip stack includes a first stack and a second stack on the first stack. The second stack constitutes a channel separate from that of the first stack.

公开(公告)号：US20220157795A1

公开(公告)日：2022-05-19

申请号：US17580047

申请日：2022-01-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： TAE-YOUNG LEE ,  DONGOK KWAK ,  BOSEONG KIM ,  SANG SUB SONG ,  JOONYOUNG OH

IPC: H01L25/10 ,  H01L23/538 ,  H01L23/552 ,  H01L23/00 ,  H01L25/065 ,  H01L21/48 ,  H01L21/56 ,  H01L21/683 ,  H01L21/78 ,  H01L25/00 ,  H01L23/31

Abstract: A method of fabricating a semiconductor package includes preparing a panel package including a redistribution substrate, a connection substrate and a plurality of lower semiconductor chips; sawing the panel package to form a plurality of separated strip packages each of which includes the sawed redistribution substrate, at least two of the lower semiconductor chips, and the sawed connection substrate; and providing a plurality of upper semiconductor chips on one of the strip packages to electrically connect the upper semiconductor chips to the sawed connection substrate.

公开(公告)号：US20210212206A1

公开(公告)日：2021-07-08

申请号：US17029222

申请日：2020-09-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： IN-JAE LEE ,  YOUNGDONG KIM ,  SANG SUB SONG ,  KI-HONG JEONG

IPC: H05K1/11 ,  H01R12/71

Abstract: A card-type solid state drive (SSD) including: a substrate that has a first surface and a second surface facing each other; a memory controller and a nonvolatile memory device that are on the first surface; a plurality of functional terminals on the second surface; and a plurality of thermal terminals on the second surface, wherein the functional terminals include first-row functional terminals, second-row functional terminals, and third-row functional terminals, wherein at least one of the first-row functional terminals, at least one of the second-row functional terminals, and at least one of the third-row functional terminals are electrically connected to the memory controller Or the nonvolatile memory device, and wherein the thermal terminals are not electrically connected to the memory controller or the nonvolatile memory device.

公开(公告)号：US20240194640A1

公开(公告)日：2024-06-13

申请号：US18331977

申请日：2023-06-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： SEONGHO YOON ,  SANG SUB SONG

IPC: H01L25/065 ,  H01L23/00 ,  H10B80/00

CPC classification number: H01L25/0652 ,  H01L24/48 ,  H10B80/00 ,  H01L2224/48137 ,  H01L2224/48145 ,  H01L2224/48229 ,  H01L2924/1431 ,  H01L2924/1438 ,  H01L2924/15165

Abstract: A substrate for a semiconductor package includes a semiconductor chip mounting region; a bonding terminal region including at least one bonding terminal; at least one plating line extending across the semiconductor chip mounting region; a plating line prohibition region at an opposite side of the bonding terminal region from the semiconductor chip mounting region; and a plating line removal region that is between the bonding terminal region and the semiconductor chip mounting region and is free of a portion of the plating line so that each of the at least one bonding terminal is electrically isolated.