Dissection method for layout patterns in semiconductor device, optical proximity correction method including the same and method of manufacturing semiconductor device including the same

    公开(公告)号:US11415896B2

    公开(公告)日:2022-08-16

    申请号:US16369932

    申请日:2019-03-29

    Inventor: Sang-Wook Kim

    Abstract: In a dissection method for layout patterns in a semiconductor device, a design layout is divided into a plurality of patches. A plurality of first dissection points for target layout patterns in the target patch and neighboring layout patterns in the neighboring patches are set based on vertexes of the target and neighboring layout patterns. At least one second dissection point for at least one exceptional layout pattern is set. The at least one exceptional layout pattern is a layout pattern in which the first dissection points are not set and which extends to pass through boundaries of one patch. A plurality of third dissection points for the target layout patterns and the neighboring layout patterns are set based on the first and second dissection points. The target layout patterns are divided into a plurality of target segments based on the first, second and third dissection points.

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