公开(公告)号：US20230161455A1

公开(公告)日：2023-05-25

申请号：US18151772

申请日：2023-01-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Woojoo KIM ,  Seonghan JANG

IPC: G06F3/0482 ,  G06F3/04817 ,  G06F9/451 ,  G06F9/54

CPC classification number: G06F3/0482 ,  G06F3/04817 ,  G06F9/451 ,  G06F9/541

Abstract: A display driving circuit according to an example embodiment of the inventive concept is disclosed. A display driving circuit may include an interface configured to receive a synchronization packet and image data from the outside; a memory configured to receive the image data from the interface in the command mode; a synchronization controller configured to receive the synchronization packet and generate a flag control signal and an internal synchronization signal; a flag generator configured to generate a first flag signal and a second flag signal; and an image controller configured to receive the image data from the memory in the command mode, receive the image data from the interface in the video mode, wherein the synchronization controller is configured to calculate a delay time between a generation time of the first flag signal and a reception time of the synchronization packet, and is configured to adjust a generation time of the second flag signal.

公开(公告)号：US20220180841A1

公开(公告)日：2022-06-09

申请号：US17543000

申请日：2021-12-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Woojoo KIM ,  Seonghan JANG

IPC: G09G5/12

Abstract: A display driving circuit according to an example embodiment of the inventive concept is disclosed. A display driving circuit may include an interface configured to receive a synchronization packet and image data from the outside; a memory configured to receive the image data from the interface in the command mode; a synchronization controller configured to receive the synchronization packet and generate a flag control signal and an internal synchronization signal; a flag generator configured to generate a first flag signal and a second flag signal; and an image controller configured to receive the image data from the memory in the command mode, receive the image data from the interface in the video mode, wherein the synchronization controller is configured to calculate a delay time between a generation time of the first flag signal and a reception time of the synchronization packet, and is configured to adjust a generation time of the second flag signal.