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公开(公告)号：US20210397207A1
公开(公告)日：2021-12-23
申请号：US17167152
申请日：2021-02-04
Applicant: Samsung Electronics Co., Ltd.
Inventor： Seongwon JOO , Jeongkyun WOO , Jeongyeol BAE
Abstract: An LDO regulator includes an error amplifier, a power transistor, a monitoring circuit and/or an adaptive pole adjusting circuit (APAC). The error amplifier compares a reference voltage and a feedback voltage to generate a first error voltage based on the comparison. The power transistor including a gate coupled to an output terminal of the buffer, regulates an input voltage based on a second error voltage which is generated based on the first error voltage to provide an output voltage to an output node. The monitoring circuit, connected to the output terminal of the buffer in parallel with the power transistor, generates a control voltage associated with a load current. The APAC, connected between the output terminal of the error amplifier and the ground voltage, selectively connects an adjusting capacitor between the output terminal of the error amplifier and the ground voltage in response to the control voltage.
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