公开(公告)号：US20240422996A1

公开(公告)日：2024-12-19

申请号：US18413281

申请日：2024-01-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Bon Jae Koo ,  Seul Ji Song ,  Hwa Yeong Lee

IPC: H10B99/00

Abstract: A nonvolatile memory device may include a substrate, a plurality of gate electrodes stacked on the substrate, a first conductive pillar that extends in a first direction and intersects the gate electrodes, a second conductive pillar that extends in the first direction and intersects the gate electrodes, the second conductive pillar being spaced apart from the first conductive pillar, an information storage film between the first conductive pillar and each of the gate electrodes and between the second conductive pillar and each of the gate electrodes, the information storage film including chalcogenide, a conductive layer spaced apart from the gate electrodes in the first direction, a first charge dissipation layer between the first conductive pillar and the conductive layer, and a second charge dissipation layer between the second conductive pillar and the conductive layer, the second charge dissipation layer being spaced apart from the first charge dissipation layer.

公开(公告)号：US10916584B2

公开(公告)日：2021-02-09

申请号：US16513925

申请日：2019-07-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seul Ji Song ,  Il Mok Park ,  Kyu Sul Park

IPC: H01L27/24 ,  H01L45/00

Abstract: A semiconductor device including: first conductive lines on a substrate and extending in a first direction; second conductive lines on the first conductive lines and extending in a second direction; data storage structures between the first and second conductive lines, wherein each of the data storage structures includes a lower data storage electrode, a data storage pattern, and an upper data storage electrode, wherein a width of an upper portion of the lower data storage electrode is smaller than a width of a lower portion of the lower data storage electrode, a width of an upper portion of the data storage pattern is greater than a width of a lower portion of the data storage pattern, and the width of the upper portion of the lower data storage electrode is different from the width of the lower portion of the data storage pattern.