公开(公告)号：US11450610B2

公开(公告)日：2022-09-20

申请号：US16876600

申请日：2020-05-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seung Hyun ,  Dongug Ko ,  Joohee Park ,  Juhak Song ,  Jongseon Ahn ,  Sungwon Cho

IPC: H01L23/535 ,  H01L27/11556 ,  H01L27/11582 ,  H01L23/522 ,  H01L21/768 ,  H01L23/528

Abstract: A vertical semiconductor device may include may include a substrate, a stacked structure, an insulating interlayer, a buffer pattern and a first contact plug. The stacked structure may include insulation patterns and conductive patterns stacked on each other on the substrate. The conductive patterns may extend in a first direction parallel to an upper surface of the substrate, and edges of the conductive patterns may have a staircase shape. The conductive patterns may include pad patterns defined by exposed upper surfaces of the conductive patterns. The insulating interlayer may cover the stacked structure. The buffer pattern may be on the insulating interlayer. The first contact plug may pass through the buffer pattern and the insulating interlayer. The first contact plug may contact one of the pad patterns. The buffer pattern may reduce defects from forming the first contact plug.

公开(公告)号：US11171151B2

公开(公告)日：2021-11-09

申请号：US16354448

申请日：2019-03-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Shin-Hwan Kang ,  Sun-Il Shim ,  Seung Hyun

IPC: H01L23/535 ,  H01L27/11582 ,  H01L29/423 ,  H01L29/45 ,  H01L27/11573

Abstract: A vertical memory device includes first gate electrodes stacked on a cell region of a substrate and spaced apart from each other in a vertical direction substantially perpendicular to an upper surface of the substrate, a channel extending through the first gate electrodes and extending in the vertical direction, a first contact plug structure contacting a corresponding one of the first gate electrodes, extending in the vertical direction, and including a first metal pattern, a first barrier pattern covering a lower surface and a sidewall of the first metal pattern and a first metal silicide pattern covering a lower surface and a sidewall of the first barrier pattern, and a second contact plug structure extending in the vertical direction on a peripheral circuit region of the substrate and including a second metal pattern and a second barrier pattern covering a lower surface and a sidewall of the second metal pattern.

公开(公告)号：US12048156B2

公开(公告)日：2024-07-23

申请号：US17450726

申请日：2021-10-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Shin-Hwan Kang ,  Sun-Il Shim ,  Seung Hyun

IPC: H10B43/27 ,  H01L23/535 ,  H01L29/423 ,  H01L29/45 ,  H10B43/40

CPC classification number: H10B43/27 ,  H01L23/535 ,  H01L29/4234 ,  H01L29/456 ,  H10B43/40

Abstract: A vertical memory device includes first gate electrodes stacked on a cell region of a substrate and spaced apart from each other in a vertical direction substantially perpendicular to an upper surface of the substrate, a channel extending through the first gate electrodes and extending in the vertical direction, a first contact plug structure contacting a corresponding one of the first gate electrodes, extending in the vertical direction, and including a first metal pattern, a first barrier pattern covering a lower surface and a sidewall of the first metal pattern and a first metal silicide pattern covering a lower surface and a sidewall of the first barrier pattern, and a second contact plug structure extending in the vertical direction on a peripheral circuit region of the substrate and including a second metal pattern and a second barrier pattern covering a lower surface and a sidewall of the second metal pattern.