公开(公告)号：US11854976B2

公开(公告)日：2023-12-26

申请号：US17740453

申请日：2022-05-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sanghoon Baek ,  Seung Young Lee

IPC: H01L23/528 ,  H01L27/02 ,  H01L23/538 ,  H01L21/8238 ,  H01L21/8234 ,  H01L27/118

CPC classification number: H01L23/5283 ,  H01L21/823871 ,  H01L23/528 ,  H01L23/5286 ,  H01L23/5386 ,  H01L27/0207 ,  H01L21/823475 ,  H01L27/11807 ,  H01L2027/11862 ,  H01L2027/11875 ,  H01L2027/11888

Abstract: A semiconductor device is provided. The semiconductor device includes a first-direction plurality of wirings extending in a first direction, and a second-direction plurality of wiring extending in a second direction intersecting the first direction. The first-direction plurality of wirings that extend in the first direction includes gate wirings spaced apart from each other in the second direction by a gate pitch, first wirings above the gate wirings spaced apart from each other in the second direction by a first pitch, second wirings above the first wirings spaced apart from each other in the second direction by a second pitch, and third wirings above the second wirings spaced apart from each other in the second direction by a third pitch. A ratio between the gate pitch and the second pitch is 6:5.

公开(公告)号：US11810920B2

公开(公告)日：2023-11-07

申请号：US17027211

申请日：2020-09-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ji Su Yu ,  Jae-Ho Park ,  Sanghoon Baek ,  Hyeon Gyu You ,  Seung Young Lee ,  Seung Man Lim

IPC: H01L27/02 ,  H01L27/118

CPC classification number: H01L27/11807 ,  H01L27/0207 ,  H01L2027/11861 ,  H01L2027/11866 ,  H01L2027/11885

Abstract: An integrated circuit includes a first standard cell including a first p-type transistor, a first n-type transistor, a first gate stack intersecting first and second active regions, first extended source/drain contacts on a first side of the first gate stack, a first normal source/drain contact on a second side of the first gate stack, a first gate via connected to the first gate stack, and a first source/drain via connected to the first normal source/drain contact, a second standard cell adjacent the first standard cell and including a second p-type transistor, a second n-type transistor, a second gate stack intersecting the first and second active regions, and a second gate via connected to the second gate stack, an input wiring connected to the first gate via, and an output wiring at a same level as the input wiring to connect the first source/drain via and the second gate via.

公开(公告)号：US11695002B2

公开(公告)日：2023-07-04

申请号：US17720153

申请日：2022-04-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sanghoon Baek ,  Myung Gil Kang ,  Jae-Ho Park ,  Seung Young Lee

IPC: H01L27/02 ,  H01L27/092 ,  H01L29/786 ,  H01L29/06 ,  H01L29/423 ,  H01L27/118

CPC classification number: H01L27/0207 ,  H01L27/092 ,  H01L27/11807 ,  H01L29/0649 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/78696

Abstract: An integrated circuit includes first and second active regions, first and second standard cells on the first active region and the second active region, and a filler cell between the first and second standard cells and including first and second insulating isolations. The filler cell has a one-pitch dimension. The first and second insulating isolations are spaced the one-pitch dimension apart from each other. The first insulating isolation of the filler cell is disposed at a first boundary between the first standard cell and the filler cell. The second insulating isolation of the filler cell is disposed at a second boundary between the second standard cell and the filler cell. The first and second insulating isolations separate at least a part of the first active region, and at least a part of the second active region.

公开(公告)号：US11329039B2

公开(公告)日：2022-05-10

申请号：US16842053

申请日：2020-04-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sanghoon Baek ,  Myung Gil Kang ,  Jae-Ho Park ,  Seung Young Lee

IPC: H01L27/02 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L27/118

Abstract: An integrated circuit includes first and second active regions, first and second standard cells on the first active region and the second active region, and a filler cell between the first and second standard cells and including first and second insulating isolations. The filler cell has a one-pitch dimension. The first and second insulating isolations are spaced the one-pitch dimension apart from each other. The first insulating isolation of the filler cell is disposed at a first boundary between the first standard cell and the filler cell. The second insulating isolation of the filler cell is disposed at a second boundary between the second standard cell and the filler cell. The first and second insulating isolations separate at least a part of the first active region, and at least a part of the second active region.

公开(公告)号：US11462475B2

公开(公告)日：2022-10-04

申请号：US16910748

申请日：2020-06-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sanghoon Baek ,  Seung Young Lee

IPC: H01L23/528 ,  H01L27/02 ,  H01L23/538 ,  H01L27/118 ,  H01L21/8238 ,  H01L21/8234

Abstract: A semiconductor device is provided. The semiconductor device includes a first-direction plurality of wirings extending in a first direction, and a second-direction plurality of wiring extending in a second direction intersecting the first direction. The first-direction plurality of wirings that extend in the first direction includes gate wirings spaced apart from each other in the second direction by a gate pitch, first wirings above the gate wirings spaced apart from each other in the second direction by a first pitch, second wirings above the first wirings spaced apart from each other in the second direction by a second pitch, and third wirings above the second wirings spaced apart from each other in the second direction by a third pitch. A ratio between the gate pitch and the second pitch is 6:5.