公开(公告)号：US20200019854A1

公开(公告)日：2020-01-16

申请号：US16480545

申请日：2018-02-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Arun ABRAHAM ,  Suhas Parlathaya KUDRAL ,  Balaji Srinivas HOLUR ,  Sarbojit GANGULY ,  Venkappa MALA ,  Suneel Kumar SURIMANI ,  Sharan Kumar ALLUR

IPC: G06N3/08 ,  G06F9/48 ,  G06F9/445

Abstract: The present invention describes a method of accelerating execution of one or more application tasks in a computing device using machine learning (ML) based model. According to one embodiment, a neural accelerating engine present in the computing device receives a ML input task for execution on the computing device from a user. The neural accelerating engine further retrieves a trained ML model and a corresponding optimal configuration file based on the received ML input task. Also, the current performance status of the computing device for executing the ML input task is obtained. Then, the neural accelerating engine dynamically schedules and dispatches parts of the ML input task to one or more processing units in the computing device for execution based on the retrieved optimal configuration file and the obtained current performance status of the computing device.

公开(公告)号：US20220366217A1

公开(公告)日：2022-11-17

申请号：US17864596

申请日：2022-07-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Briraj SINGH ,  Amogha UDUPA SHANKARANARAYANA GOPAL ,  Aniket DWIVEDI ,  Bharat MUDRAGADA ,  Alladi Ashok Kumar SENAPATI ,  Suhas Parlathaya KUDRAL ,  Arun ABRAHAM ,  Praveen Doreswamy NAIDU

IPC: G06N3/04

Abstract: Embodiments herein provide a method and system for network and hardware aware computing layout selection for efficient Deep Neural Network (DNN) Inference. The method comprises: receiving, by the electronic device, a DNN model to be executed, wherein the DNN model is associated with a task; dividing the DNN model into a plurality of sub-graphs, wherein each sub-graph is to be processed individually; identifying a computing unit from a plurality of computing units for execution of each sub-graph based on a complexity score; and determining a computing layout from a plurality of computing layouts for each identified computing unit, wherein the sub-graph is executed on the identified computing unit through the determined computing layout.