公开(公告)号：US20240061040A1

公开(公告)日：2024-02-22

申请号：US18450043

申请日：2023-08-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Taewoong AHN ,  Youngin PARK ,  Junyeong JANG

IPC: G01R31/3185

CPC classification number: G01R31/318536 ,  G01R31/318547

Abstract: An integrated circuit package for scan testing a semiconductor chip includes at least one first input pad configured to receive a first input signal, at least one chip connected to the first input pad, and at least one first output pad configured to receive a first output signal generated by the at least one chip, wherein each of the at least one chip includes at least one second input pad configured to receive a second input signal, a plurality of scan chains, a first test circuit and a second test circuit, which share the plurality of scan chains, and at least one second output pad configured to receive a second output signal from the first test circuit.