公开(公告)号：US11990409B2

公开(公告)日：2024-05-21

申请号：US17354593

申请日：2021-06-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Taeyong Bae ,  Hoonseok Seo

IPC: H01L23/528 ,  H01L21/768 ,  H01L23/522

CPC classification number: H01L23/5283 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/528

Abstract: Provided is a semiconductor device including a front-end-of-line (FEOL) structure and a back-end-of-line (BEOL) structure connected to the FEOL structure, wherein the FEOL structure includes at least one source/drain region and at least one gate structure, and the BEOL structure includes: a plurality of 1st fine metal lines arranged in a row with a same pitch, each of the plurality of 1st fine metal lines having a same width; and at least one 1st wide metal line formed at a side of the plurality of 1st fine metal lines, the 1st wide metal line having a width greater than the width of the 1st fine metal line, and wherein each of the plurality of 1st fine metal lines includes a material different from a material included in the 1st wide metal line.

公开(公告)号：US12218054B2

公开(公告)日：2025-02-04

申请号：US17849836

申请日：2022-06-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Taeyong Bae ,  Hoonseok Seo

IPC: H01L23/528 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532

Abstract: Integrated circuit devices and methods of forming the same are provided. The integrated circuit devices may include a first insulating layer and a plurality of metal wires on the first insulating layer. The plurality of metal wires may include a first metal wire including a first upper surface and a first lower surface that faces the first insulating layer and a second metal wire including a second upper surface and a second lower surface that faces the first insulating layer and is coplanar with the first lower surface. The first metal wire may have a first width monotonically decreasing from the first lower surface to the first upper surface, and the second metal wire may have a second width monotonically increasing from the second lower surface to the second upper surface.

公开(公告)号：US11450608B2

公开(公告)日：2022-09-20

申请号：US17066526

申请日：2020-10-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Taeyong Bae ,  Hoonseok Seo

IPC: H01L23/528 ,  H01L23/522 ,  H01L23/532 ,  H01L21/768

Abstract: Integrated circuit devices and methods of forming the same are provided. The integrated circuit devices may include a first insulating layer and a plurality of metal wires on the first insulating layer. The plurality of metal wires may include a first metal wire including a first upper surface and a first lower surface that faces the first insulating layer and a second metal wire including a second upper surface and a second lower surface that faces the first insulating layer and is coplanar with the first lower surface. The first metal wire may have a first width monotonically decreasing from the first lower surface to the first upper surface, and the second metal wire may have a second width monotonically increasing from the second lower surface to the second upper surface.

公开(公告)号：US12243820B2

公开(公告)日：2025-03-04

申请号：US18600031

申请日：2024-03-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Taeyong Bae ,  Hoonseok Seo

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/528

Abstract: Provided is a semiconductor device including a a front-end-of-line (FEOL) structure and a back-end-of-line (BEOL) structure connected to the FEOL structure, wherein the FEOL structure includes at least one source/drain region and at least one gate structure, and the BEOL structure includes: a plurality of 1st fine metal lines arranged in a row with a same pitch, each of the plurality of 1st fine metal lines having a same width; and at least one 1st wide metal line formed at a side of the plurality of 1st fine metal lines, the 1st wide metal line having a width greater than the width of the 1st fine metal line, and wherein each of the plurality of 1st fine metal lines includes a material different from a material included in the 1st wide metal line.

公开(公告)号：US20240297072A1

公开(公告)日：2024-09-05

申请号：US18662083

申请日：2024-05-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hoonseok SEO ,  Euibok Lee ,  Taeyong Bae

IPC: H01L21/768 ,  H01L21/3213 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532

CPC classification number: H01L21/76816 ,  H01L21/32139 ,  H01L21/76832 ,  H01L21/76879 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/53266

Abstract: A a method of manufacturing a semi-damascene structure of a semiconductor device includes: forming a 1st intermetal dielectric layer; forming a 1st hardmask layer and at least one 1st photoresist pattern on the 1st intermetal dielectric layer; patterning at least one via hole penetrating through the 1st hardmask layer and the 1st intermetal dielectric using the 1st photoresist pattern; removing the 1st photoresist pattern among the 1st photoresist pattern and the 1st hardmask layer; forming a metal structure in the via hole such that the metal structure fills in the vial hole and extends on the 1st hardmask layer; patterning the metal structure to form at least one 1st trench penetrating at least the metal structure at a portion where the metal structure extends on the 1st hardmask layer; and filling the 1st trench with a 2nd inter-metal layer.

公开(公告)号：US12014951B2

公开(公告)日：2024-06-18

申请号：US17390035

申请日：2021-07-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hoonseok Seo ,  Euibok Lee ,  Taeyong Bae

IPC: H01L21/768 ,  H01L21/3213 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532

CPC classification number: H01L21/76816 ,  H01L21/32139 ,  H01L21/76832 ,  H01L21/76879 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/53266

Abstract: A method of manufacturing a semi-damascene structure of a semiconductor device includes: forming a 1st intermetal dielectric layer; forming a 1st hardmask layer and at least one 1st photoresist pattern on the 1st intermetal dielectric layer; patterning at least one via hole penetrating through the 1st hardmask layer and the 1st intermetal dielectric using the 1st photoresist pattern; removing the 1st photoresist pattern among the 1st photoresist pattern and the 1st hardmask layer; forming a metal structure in the via hole such that the metal structure fills in the vial hole and extends on the 1st hardmask layer; patterning the metal structure to form at least one 1st trench penetrating at least the metal structure at a portion where the metal structure extends on the 1st hardmask layer; and filling the 1st trench with a 2nd inter-metal layer.

公开(公告)号：US11488864B2

公开(公告)日：2022-11-01

申请号：US17150557

申请日：2021-01-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Taeyong Bae ,  Hoonseok Seo ,  Euibok Lee

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532

Abstract: A semiconductor device structure includes: at least one inter-metal layer stacked in a vertical direction; and a 1st via structure penetrating the at least one inter-metal layer, wherein, in the at least one inter-metal layer, a 1st vertical side of the 1st via structure does not contact a barrier metal pattern while a 2nd vertical side of the 1st via structure opposite to the 1st vertical side of the 1st via structure contacts the barrier metal pattern.