Method of forming an integrated circuit device having an etch-stop layer between metal wires

    公开(公告)号:US12218054B2

    公开(公告)日:2025-02-04

    申请号:US17849836

    申请日:2022-06-27

    Abstract: Integrated circuit devices and methods of forming the same are provided. The integrated circuit devices may include a first insulating layer and a plurality of metal wires on the first insulating layer. The plurality of metal wires may include a first metal wire including a first upper surface and a first lower surface that faces the first insulating layer and a second metal wire including a second upper surface and a second lower surface that faces the first insulating layer and is coplanar with the first lower surface. The first metal wire may have a first width monotonically decreasing from the first lower surface to the first upper surface, and the second metal wire may have a second width monotonically increasing from the second lower surface to the second upper surface.

    Integrated circuit devices including metal wires having etch stop layers on sidewalls thereof

    公开(公告)号:US11450608B2

    公开(公告)日:2022-09-20

    申请号:US17066526

    申请日:2020-10-09

    Abstract: Integrated circuit devices and methods of forming the same are provided. The integrated circuit devices may include a first insulating layer and a plurality of metal wires on the first insulating layer. The plurality of metal wires may include a first metal wire including a first upper surface and a first lower surface that faces the first insulating layer and a second metal wire including a second upper surface and a second lower surface that faces the first insulating layer and is coplanar with the first lower surface. The first metal wire may have a first width monotonically decreasing from the first lower surface to the first upper surface, and the second metal wire may have a second width monotonically increasing from the second lower surface to the second upper surface.

    Semiconductor device with fine metal lines for BEOL structure and method of manufacturing the same

    公开(公告)号:US12243820B2

    公开(公告)日:2025-03-04

    申请号:US18600031

    申请日:2024-03-08

    Abstract: Provided is a semiconductor device including a a front-end-of-line (FEOL) structure and a back-end-of-line (BEOL) structure connected to the FEOL structure, wherein the FEOL structure includes at least one source/drain region and at least one gate structure, and the BEOL structure includes: a plurality of 1st fine metal lines arranged in a row with a same pitch, each of the plurality of 1st fine metal lines having a same width; and at least one 1st wide metal line formed at a side of the plurality of 1st fine metal lines, the 1st wide metal line having a width greater than the width of the 1st fine metal line, and wherein each of the plurality of 1st fine metal lines includes a material different from a material included in the 1st wide metal line.

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