公开(公告)号：US10963388B2

公开(公告)日：2021-03-30

申请号：US16543503

申请日：2019-08-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Vikas Sinha ,  Teik Tan ,  Tarun Nakra

IPC: G06F12/08 ,  G06F12/0862 ,  G06F12/0811 ,  G06F13/40

Abstract: According to one general aspect, an apparatus may include a multi-tiered cache system that includes at least one upper cache tier relatively closer, hierarchically, to a processor and at least one lower cache tier relatively closer, hierarchically, to a system memory. The apparatus may include a memory interconnect circuit hierarchically between the multi-tiered cache system and the system memory. The apparatus may include a prefetcher circuit coupled with a lower cache tier of the multi-tiered cache system, and configured to issue a speculative prefetch request to the memory interconnect circuit for data to be placed into the lower cache tier. The memory interconnect circuit may be configured to cancel the speculative prefetch request if the data exists in an upper cache tier of the multi-tiered cache system.