公开(公告)号：US20170140810A1

公开(公告)日：2017-05-18

申请号：US15340345

申请日：2016-11-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Won-Jun CHOI ,  Hui-Kap YANG

IPC: G11C11/406 ,  G11C7/10 ,  G11C11/4096 ,  G11C11/408 ,  G11C11/4091

CPC classification number: G11C11/40603 ,  G11C11/40607 ,  G11C11/40618

Abstract: A memory device includes a memory bank, a command control logic circuit, a row selection circuit, a refresh controller and a collision controller. The memory bank includes a plurality of memory blocks. The command control logic circuit decodes commands received from a memory controller to generate control signals. The command control logic receives an active command for an access operation during a refresh operation. The row selection circuit performs the access operation and the refresh operation with respect to the memory bank. The refresh controller controls the refresh operation. The collision controller generates a wait signal causing a delay of the access operation based on a result of a comparison of a row address associated with the access operation and a refresh address associated with the refresh operation.