Robot cleaner station
    1.
    发明授权

    公开(公告)号:US11452417B2

    公开(公告)日:2022-09-27

    申请号:US16919890

    申请日:2020-07-02

    Abstract: A robot cleaner station includes a cleaner docking portion to which a robot cleaner is docked and including an suction port in communication with a dust collector of the robot cleaner when the robot clear is docked to the cleaner docking portion, a collector including a collection chamber in which dust sucked from the dust collector through the suction port is collected, and a station suction device configured to generate a suction force to suck the dust from the dust collector to the collection chamber, and a connector configured to connect the suction port to the collection chamber. The connector includes a guide portion in communication with the suction port, a suction tube provided in the collection chamber to allow the dust which is guided by the guide portion to be sucked to the collection chamber, and a connection hose configured to connect the guide portion to the suction tube.

    Station of robot cleaner
    2.
    发明授权

    公开(公告)号:US11452418B2

    公开(公告)日:2022-09-27

    申请号:US16985942

    申请日:2020-08-05

    Abstract: A station suctioning dust from the robot cleaner includes a docking suction port connectable to a robot cleaner, a dust container to store dust from the robot cleaner, a duct connected to the docking suction port and the dust container, a holder disposed in the dust container, and to which a dust bag is mountable, and a lever configured to hinder a connection of the holder and the duct while the dust bag is in a separated state from the holder, and the lever allows the connection of the holder and the duct while the dust bag is in a mounted state to the holder.

    Apparatus, memory device, and method for multi-phase clock training

    公开(公告)号:US12198783B2

    公开(公告)日:2025-01-14

    申请号:US17959663

    申请日:2022-10-04

    Abstract: Provided are an apparatus, a memory device, and a method for multi-phase clock training. The memory device includes a clock training circuit configured to receive a clock through a first signal pin, among a plurality of signal pins and connected to a first signal line connected to the first signal pin. The clock training circuit generates a multi-phase clock upon receiving the clock, and generates a three-dimensional (3-D) duty offset code (DOC) for the multi-phase clock by simultaneously phase-sweeping between three internal clock signals in a duty adjustment step in the multi-phase clock. The memory device corrects a duty error of the multi-phase clock using the 3-D DOC.

Patent Agency Ranking