公开(公告)号：US11496753B2

公开(公告)日：2022-11-08

申请号：US17060127

申请日：2020-10-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Woojoo Kim ,  Seongmin Cheon

IPC: H04N19/184 ,  H04N19/156 ,  H04N19/426

Abstract: A display driver circuit configured to drive a display panel includes a memory, a decoder, and a controller. The memory stores first data using data from outside of the display driver circuit. The decoder decodes the stored first data. The controller generates compression data using the decoded first data. While an image based on the decoded first data is displayed on the display panel, when second data based on the data from the outside are not stored in the memory after the first data are stored in the memory, the controller controls the decoder such that the decoder does not operate and controls the memory such that the compression data are stored in the memory.

公开(公告)号：US10834411B2

公开(公告)日：2020-11-10

申请号：US16150365

申请日：2018-10-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Woojoo Kim ,  Seongmin Cheon

IPC: H04N19/184 ,  H04N19/156 ,  H04N19/426

Abstract: A display driver circuit configured to drive a display panel includes a memory, a decoder, and a controller. The memory stores first data using data from outside of the display driver circuit. The decoder decodes the stored first data. The controller generates compression data using the decoded first data. While an image based on the decoded first data is displayed on the display panel, when second data based on the data from the outside are not stored in the memory after the first data are stored in the memory, the controller controls the decoder such that the decoder does not operate and controls the memory such that the compression data are stored in the memory.

公开(公告)号：US20250104620A1

公开(公告)日：2025-03-27

申请号：US18887681

申请日：2024-09-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Changju Lee ,  Woojoo Kim ,  Haksong Kim ,  Kyounghwan Kwon

IPC: G09G3/3208

Abstract: A display driving circuit operating in video mode is described. The display driving circuit includes an interface configured to receive, from an external source, sync signals and image data corresponding to each of a plurality of frames, a data processor configured to receive the image data from the interface and convert the image data, and a timing controller configured to generate internal control signals for driving a driver circuit based on the sync signals and the image data. The internal control signals are configured to be output only when the sync signals and signals corresponding to the image data are input simultaneously, and panel driving signals are configured to be output when the internal control signals are output.

公开(公告)号：US12087195B2

公开(公告)日：2024-09-10

申请号：US17679436

申请日：2022-02-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Taek Su Kwon ,  Woojoo Kim ,  Dongwook Suh

IPC: G09G3/3275 ,  G09G3/20

CPC classification number: G09G3/20 ,  G09G2310/027 ,  G09G2310/0291 ,  G09G2320/0252

Abstract: Disclosed is a source amplifier which includes a first circuit that outputs a first current to an output terminal of the source amplifier by amplifying an input voltage, and a second circuit that is connected with the first circuit and outputs a second current to the output terminal based on the input voltage. The second circuit includes a third circuit that adjusts a level of the second current in response to an enable signal.

公开(公告)号：US12081776B2

公开(公告)日：2024-09-03

申请号：US18050515

申请日：2022-10-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Woojoo Kim ,  Seongmin Cheon

IPC: H04N19/184 ,  H04N19/156 ,  H04N19/426

CPC classification number: H04N19/184 ,  H04N19/156 ,  H04N19/428

Abstract: A display driver circuit configured to drive a display panel includes a memory, a decoder, and a controller. The memory stores first data using data from outside of the display driver circuit. The decoder decodes the stored first data. The controller generates compression data using the decoded first data. While an image based on the decoded first data is displayed on the display panel, when second data based on the data from the outside are not stored in the memory after the first data are stored in the memory, the controller controls the decoder such that the decoder does not operate and controls the memory such that the compression data are stored in the memory.

公开(公告)号：US12000594B2

公开(公告)日：2024-06-04

申请号：US17301359

申请日：2021-03-31

Applicant: Samsung Electronics Co., Ltd.

Inventor： Heesoo Jeong ,  Woojoo Kim ,  Sihwan Kim ,  Hoseung Seo ,  Dongmyeong Lee ,  Hongman Chang

IPC: F24C15/02 ,  F24C15/08

CPC classification number: F24C15/023 ,  F24C15/028 ,  F24C15/08

Abstract: A home appliance includes a body and a door. The body includes a chamber. The door is configured to open and close the chamber. The door includes an upper flange forming an upper surface of the door. The door also includes a side flange forming a side surface of the door. The door further includes a support flange formed by being bent at an upper end of the side flange. The support flange includes a support portion that is configured to come in contact with the upper flange and a bending portion connecting the side flange to the support portion. The upper flange is arranged on the support portion such that one end of the upper flange is located on an upper portion of the bending portion.

公开(公告)号：US11551642B2

公开(公告)日：2023-01-10

申请号：US17543000

申请日：2021-12-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Woojoo Kim ,  Seonghan Jang

IPC: G09G3/20 ,  G09G5/12

Abstract: A display driving circuit according to an example embodiment of the inventive concept is disclosed. A display driving circuit may include an interface configured to receive a synchronization packet and image data from the outside; a memory configured to receive the image data from the interface in the command mode; a synchronization controller configured to receive the synchronization packet and generate a flag control signal and an internal synchronization signal; a flag generator configured to generate a first flag signal and a second flag signal; and an image controller configured to receive the image data from the memory in the command mode, receive the image data from the interface in the video mode, wherein the synchronization controller is configured to calculate a delay time between a generation time of the first flag signal and a reception time of the synchronization packet, and is configured to adjust a generation time of the second flag signal.