公开(公告)号：US12199634B2

公开(公告)日：2025-01-14

申请号：US18058388

申请日：2022-11-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yoochang Eun ,  Woongjae Han

IPC: H03M13/11

Abstract: There is provided a decoding apparatus for decoding a low density parity check (LDPC) code, wherein the decoding apparatus includes a memory a memory configured to store a scheduling table indicating a desired processing order of a plurality of rows included in a parity check matrix and a plurality of columns included in each of the rows of the parity check matrix, and processing circuitry configured to decode the LDPC code based on the scheduling table, the decoding including performing processing on at least one column included in a second scheduled row of the parity check matrix before processing of all columns included in a first scheduled row of the parity check matrix has been completed.