公开(公告)号：US20180358345A1

公开(公告)日：2018-12-13

申请号：US15787244

申请日：2017-10-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： YUBO QIAN ,  Byung-Sung KIM ,  CHUL-HONG PARK ,  Haewang LEE

IPC: H01L27/02 ,  H01L23/528 ,  H01L23/522 ,  G06F17/50 ,  H01L21/8238 ,  H01L27/092 ,  H03K19/0948 ,  H01L23/535

CPC classification number: H01L27/0207 ,  G06F17/5072 ,  G06F17/5077 ,  H01L21/823821 ,  H01L21/823871 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/5286 ,  H01L23/535 ,  H01L27/092 ,  H01L27/0924 ,  H01L27/11807 ,  H01L29/66545 ,  H01L29/7848 ,  H01L2027/11875 ,  H03K19/0948

Abstract: Disclosed are a semiconductor device and a method of manufacturing the same. The semiconductor device includes first and second logic cells adjacent to each other in a first direction on a substrate, a gate electrode extending in the first direction in each of the first and second logic cells, a power line extending in a second direction at a boundary between the first and second logic cells, and a connection structure electrically connecting the power line to an active pattern of the first logic cell and to an active pattern of the second logic cell. The connection structure lies below the power line and extends from the first logic cell to the second logic cell. A top surface of the connection structure is at a higher level than that of a top surface of the gate electrode.