公开(公告)号：US11068636B2

公开(公告)日：2021-07-20

申请号：US16835423

申请日：2020-03-31

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yoonjae Hwang ,  Sungwook Moon

IPC: G06F30/392 ,  H01L23/498 ,  H01L23/522 ,  G06F30/373 ,  H01L25/065 ,  H01L25/00 ,  H01L21/48

Abstract: A design method for a semiconductor package including a first chip, a second chip, a 2.5 dimensional (2.5D) interposer, a package substrate, and a board includes generating a layout including the 2.5D interposer on the package substrate and the first and second chips individually arranged on the 2.5D interposer, based on design information; analyzing signal integrity and power integrity between the first and second chips from the layout; analyzing signal integrity or power integrity between the first chip and at least one third chip on the board from the layout; and determining whether to modify the layout based on the analysis results.