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公开(公告)号：US20220123759A1
公开(公告)日：2022-04-21
申请号：US17346220
申请日：2021-06-12
Applicant: Samsung Electronics Co., Ltd.
Inventor： Byungsuk Woo , Younguk Chang , Yongho Cho
Abstract: A multi-level signal generator includes a receiving circuit, a setting circuit, a data bit generating circuit and a digital-to-analog converter. The receiving circuit generates a first data bit based on an input data signal having two voltage levels that are different from each other. The setting circuit generates a flag signal based on a command signal. The flag signal is changed depending on an operation mode. The data bit generating circuit generates a plurality of internal bits based on the first data bit, selects at least one of the plurality of internal bits based on the flag signal, and outputs the selected internal bit as at least one additional data bit. The digital-to-analog converter generates an output data signal that is a multi-level signal having three or more voltage levels different from each other based on the first data bit and the at least one additional data bit.
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公开(公告)号：US11755234B2
公开(公告)日：2023-09-12
申请号：US17394488
申请日：2021-08-05
Applicant: Samsung Electronics Co., Ltd.
Inventor： Byungsuk Woo , Younguk Chang , Yongho Cho
IPC: G06F3/06
CPC classification number: G06F3/0653 , G06F3/0604 , G06F3/0679
Abstract: In a method of generating a signal for test in a memory device configured to output a multi-level signal, an operation mode is set to a first test mode. During the first test mode, first data bits included in a plurality of test data are arranged based on a first scheme. Each of the plurality of test data includes two or more data bits. During the first test mode, a first test result signal having two voltage levels is generated based on the first data bits according to the first scheme. The operation mode is set to a second test mode during which second data bits included in the plurality of test data are arranged based on a second scheme. During the second test mode, a second test result signal having the two voltage levels is generated based on the second data bits according to the second scheme.
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公开(公告)号：US11569836B2
公开(公告)日：2023-01-31
申请号：US17346220
申请日：2021-06-12
Applicant: Samsung Electronics Co., Ltd.
Inventor： Byungsuk Woo , Younguk Chang , Yongho Cho
Abstract: A multi-level signal generator includes a receiving circuit, a setting circuit, a data bit generating circuit and a digital-to-analog converter. The receiving circuit generates a first data bit based on an input data signal having two voltage levels that are different from each other. The setting circuit generates a flag signal based on a command signal. The flag signal is changed depending on an operation mode. The data bit generating circuit generates a plurality of internal bits based on the first data bit, selects at least one of the plurality of internal bits based on the flag signal, and outputs the selected internal bit as at least one additional data bit. The digital-to-analog converter generates an output data signal that is a multi-level signal having three or more voltage levels different from each other based on the first data bit and the at least one additional data bit.
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