公开(公告)号：US20180276052A1

公开(公告)日：2018-09-27

申请号：US15670370

申请日：2017-08-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jae-Youl KIM ,  Yun-Gwan YU

IPC: G06F9/52 ,  G06F11/30 ,  G06F11/36

CPC classification number: G06F9/524 ,  G06F11/22 ,  G06F11/3089 ,  G06F11/362 ,  G06F11/3648 ,  G06F13/36

Abstract: A system includes a plurality of hardware blocks, a deadlock detector and an interconnect device. The hardware blocks include a processor executing instructions and a storage device storing data. The deadlock detector monitors operations of a target hardware block among the plurality of hardware blocks in realtime to store debugging information in the storage device. The interconnect device electrically connects the deadlock detector and the plurality of hardware blocks. The interconnect device includes a system bus electrically connecting the plurality of hardware blocks and a debugging bus electrically connecting the deadlock detector to the target hardware block and the storage device. The interconnect device includes a system bus electrically connecting the plurality of hardware blocks and a debugging bus electrically connecting the deadlock detector to the target hardware block and the storage device.