公开(公告)号：US20250126799A1

公开(公告)日：2025-04-17

申请号：US18673528

申请日：2024-05-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kang-Oh YUN ,  Yunjo LEE ,  Dongjin LEE ,  Jaeduk LEE

IPC: H10B43/40 ,  H10B41/27 ,  H10B41/41 ,  H10B43/27

Abstract: A semiconductor device may include a substrate containing first to third doping regions, first and second gate structures between the first and second doping regions, and a gate separation layer between the first and second gate structures. Each of the first and second gate structures may include a first gate dielectric layer, a first gate conductive layer on the first gate dielectric layer, and a second gate conductive layer between the gate separation layer and the first gate conductive layer. The gate separation layer may include a first sidewall in contact with the first gate structure and a second sidewall in contact with the second gate structure. A top surface of the gate separation layer may be at a same level as a top surface of the second gate conductive layer.