Low power mode with read sequence adjustment

    公开(公告)号:US12057157B2

    公开(公告)日:2024-08-06

    申请号:US17690332

    申请日:2022-03-09

    CPC classification number: G11C11/4096 G11C11/4074 G11C11/4076

    Abstract: An apparatus disclosed herein comprises: a plurality of memory cells and a control circuit coupled to the plurality of memory cells. The control circuit is configured to: determine whether the apparatus is in low power mode; in response to determining that the apparatus is in low power mode, perform a normal order read operation on a set of memory cells of the plurality of memory cells; and in response to determining that the apparatus is not in low power mode, perform a reverse order read operation on the set of memory cells of the plurality of memory cells.

    LOW POWER MODE WITH READ SEQUENCE ADJUSTMENT

    公开(公告)号:US20230290403A1

    公开(公告)日:2023-09-14

    申请号:US17690332

    申请日:2022-03-09

    CPC classification number: G11C11/4096 G11C11/4074 G11C11/4076

    Abstract: An apparatus disclosed herein comprises: a plurality of memory cells and a control circuit coupled to the plurality of memory cells. The control circuit is configured to: determine whether the apparatus is in low power mode; in response to determining that the apparatus is in low power mode, perform a normal order read operation on a set of memory cells of the plurality of memory cells; and in response to determining that the apparatus is not in low power mode, perform a reverse order read operation on the set of memory cells of the plurality of memory cells.

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