公开(公告)号：US20120017187A1

公开(公告)日：2012-01-19

申请号：US12835621

申请日：2010-07-13

申请人： Satish Padmanabhan ,  Plus Ng ,  Anand Pandurangan ,  Suresh Kadiyala ,  Ananth Durbha ,  Tak Shigihara

发明人： Satish Padmanabhan ,  Plus Ng ,  Anand Pandurangan ,  Suresh Kadiyala ,  Ananth Durbha ,  Tak Shigihara

IPC分类号： G06F9/455 ,  G06F17/50

CPC分类号： G06F17/505 ,  G06F17/5022 ,  G06F17/5045

摘要： Systems and methods are disclosed to automatically design a custom integrated circuit based on algorithmic process or code as input and using highly automated tools that requires virtually no human involvement is disclosed. The method includes receiving a specification of the custom integrated circuit including computer readable code and one or more constraints on the custom integrated circuit; automatically generating a computer architecture for the computer readable code that best fits the constraints; automatically determining an instruction execution sequence based on the code profile and reassigning or delaying the instruction sequence to spread operation over one or more processing blocks to reduce hot spots; continuously evaluating and optimizing one or more factors including physical implementation, and local and global area, timing, or power at an architecture level above RTL or gate-level synthesis; automatically generating a software development kit (SDK) and the associated firmware automatically to execute the computer readable code on the custom integrated circuit; automatically generating associated test suites and vectors for the computer readable code on the custom integrated circuit; and automatically synthesizing the designed architecture and generating a computer readable description of the custom integrated circuit for semiconductor fabrication.

摘要翻译： 公开了系统和方法，以基于算法过程或代码作为输入自动设计定制集成电路，并且使用几乎不需要人为参与的高度自动化的工具。 该方法包括接收包括计算机可读代码和定制集成电路上的一个或多个约束的定制集成电路的规范; 自动生成最适合约束的计算机可读代码的计算机体系结构; 基于代码简档自动确定指令执行序列，并重新分配或延迟指令序列以在一个或多个处理块上扩展操作以减少热点; 连续评估和优化一个或多个因素，包括物理实现，以及在RTL或门级合成之上的架构级别的本地和全局区域，时序或功率; 自动生成软件开发工具包（SDK）和相关固件，以执行定制集成电路上的计算机可读代码; 为定制集成电路上的计算机可读代码自动生成相关的测试套件和向量; 并自动合成设计的架构并生成用于半导体制造的定制集成电路的计算机可读描述。

公开(公告)号：US08370784B2

公开(公告)日：2013-02-05

申请号：US12835621

申请日：2010-07-13

申请人： Satish Padmanabhan ,  Plus Ng ,  Anand Pandurangan ,  Suresh Kadiyala ,  Ananth Durbha ,  Tak Shigihara

发明人： Satish Padmanabhan ,  Plus Ng ,  Anand Pandurangan ,  Suresh Kadiyala ,  Ananth Durbha ,  Tak Shigihara

IPC分类号： G06F9/455 ,  G06F17/50

CPC分类号： G06F17/505 ,  G06F17/5022 ,  G06F17/5045

摘要： Systems and methods are disclosed to automatically design a custom integrated circuit based on algorithmic process or code as input and using highly automated tools that requires virtually no human involvement is disclosed. The method includes receiving a specification of the custom integrated circuit including computer readable code and one or more constraints on the custom integrated circuit; automatically generating a computer architecture for the computer readable code that best fits the constraints; automatically determining an instruction execution sequence based on the code profile and reassigning or delaying the instruction sequence to spread operation over one or more processing blocks to reduce hot spots; continuously evaluating and optimizing one or more factors including physical implementation, and local and global area, timing, or power at an architecture level above RTL or gate-level synthesis; automatically generating a software development kit (SDK) and the associated firmware automatically to execute the computer readable code on the custom integrated circuit; automatically generating associated test suites and vectors for the computer readable code on the custom integrated circuit; and automatically synthesizing the designed architecture and generating a computer readable description of the custom integrated circuit for semiconductor fabrication.

摘要翻译： 公开了系统和方法，以基于算法过程或代码作为输入自动设计定制集成电路，并且使用几乎不需要人为参与的高度自动化的工具。 该方法包括接收包括计算机可读代码和定制集成电路上的一个或多个约束的定制集成电路的规范; 自动生成最适合约束的计算机可读代码的计算机体系结构; 基于代码简档自动确定指令执行序列，并重新分配或延迟指令序列以在一个或多个处理块上扩展操作以减少热点; 连续评估和优化一个或多个因素，包括物理实现，以及在RTL或门级合成之上的架构级别的本地和全局区域，时序或功率; 自动生成软件开发工具包（SDK）和相关固件，以执行定制集成电路上的计算机可读代码; 为定制集成电路上的计算机可读代码自动生成相关的测试套件和向量; 并自动合成设计的架构并生成用于半导体制造的定制集成电路的计算机可读描述。

公开(公告)号：US08516416B1

公开(公告)日：2013-08-20

申请号：US13603421

申请日：2012-09-05

申请人： Ananth Durbha ,  Satish Padmanabhan ,  Plus Ng

发明人： Ananth Durbha ,  Satish Padmanabhan ,  Plus Ng

IPC分类号： G06F17/50

CPC分类号： G06F17/505

摘要： Systems and methods are disclosed to automatically synthesize a custom integrated circuit by encoding architecture level knowledge in a data model to generate and pass new constraints for physical synthesis of a chip specification uniquely customized to computer readable code. The system receives a look-ahead cost function during architecture optimization consistent with cost observed later in the flow after detailed physical synthesis is performed. The look-ahead cost function is generated from a prior iteration and supplied to a subsequent iteration through the data model.

摘要翻译： 公开了系统和方法，以通过在数据模型中编码架构级知识来自动合成定制集成电路，以生成和传递用于物理合成针对计算机可读代码独特定制的芯片规范的新约束。 在进行详细的物理合成之后，系统在架构优化期间接收与之前流程中观察到的成本一致的预先成本函数。 先行成本函数是从先前的迭代生成的，并通过数据模型提供给后续的迭代。

公开(公告)号：US20120017196A1

公开(公告)日：2012-01-19

申请号：US12835631

申请日：2010-07-13

申请人： Plus Ng ,  Suresh Kadiyala ,  Satish Padmanabhan

发明人： Plus Ng ,  Suresh Kadiyala ,  Satish Padmanabhan

IPC分类号： G06F9/44 ,  G06F9/45

CPC分类号： G06F17/505

摘要： Systems and methods are disclosed to automatically generate a custom integrated circuit (IC) design by receiving a specification of the custom IC including computer readable code to be executed by the custom IC; generating an abstraction of the IC as a system, processor architecture and micro-architecture (SAMA) representation; providing the SAMA representation to a data model having at least an architecture optimization view, a physical design view, and a software tool view; optimizing the processor architecture by iteratively updating the SAMA representation and the data model to automatically generate a processor architecture uniquely customized to the computer readable code which satisfies one or more constraints; and synthesizing the generated architecture into a computer readable description of the custom integrated circuit for semiconductor fabrication. The foregoing can be done with no or minimal human involvement.

摘要翻译： 公开了系统和方法，通过接收包括由定制IC执行的计算机可读代码的定制IC的规范来自动生成定制集成电路（IC）设计; 生成作为系统，处理器架构和微架构（SAMA）表示的IC的抽象; 向至少具有架构优化视图，物理设计视图和软件工具视图的数据模型提供SAMA表示; 通过迭代地更新SAMA表示和数据模型来优化处理器架构，以自动生成独特地定制为满足一个或多个约束的计算机可读代码的处理器架构; 以及将生成的架构合成到用于半导体制造的定制集成电路的计算机可读描述中。 前述可以在没有或最少的人参与的情况下完成。