公开(公告)号：US20080230820A1

公开(公告)日：2008-09-25

申请号：US12014020

申请日：2008-01-14

申请人： Satoshi Maeda ,  Hidehiro Harata ,  Hiroyuki Kono

发明人： Satoshi Maeda ,  Hidehiro Harata ,  Hiroyuki Kono

IPC分类号： H01L29/94

CPC分类号： H01L29/94 ,  H01L23/5223 ,  H01L27/0805 ,  H01L2924/0002 ,  H01L2924/00

摘要： Coexistence of the realization of high-capacity of a capacitive element and the area reduction of a semiconductor device is aimed at. A plurality of capacitive elements from which a kind differs mutually are accumulated and arranged on a semiconductor substrate, and they are connected in parallel. These capacitive elements are arranged to the same plane region, and make a plane size almost the same. A lower capacitive element is an MOS type capacitive element which uses as both electrodes the n-type semiconductor region formed in the semiconductor substrate, and the upper electrode formed via the insulation film on the n-type semiconductor region. The MIM type capacitive element formed with the pattern of the comb-type of a wiring is arranged in the upper part of a lower capacitive element, and this is connected with a lower capacitive element in parallel.

摘要翻译： 旨在实现电容元件的大容量的实现和半导体器件的面积缩小的共存。 一种不同的电容元件被累积并布置在半导体衬底上，它们并联连接。 这些电容元件被布置在相同的平面区域上，并且使得平面尺寸几乎相同。 低电容性元件是MOS型电容元件，其使用形成在半导体衬底中的n型半导体区域作为两个电极，并且通过n型半导体区域上的绝缘膜形成上电极。 形成有梳状梳状布线的MIM型电容元件布置在下部电容元件的上部，并且与下部电容元件并联连接。