公开(公告)号：US20110239179A1

公开(公告)日：2011-09-29

申请号：US13046752

申请日：2011-03-13

申请人： Satoshi SHIBATANI ,  Ryoji ISHIKAWA ,  Kenta SUTO

发明人： Satoshi SHIBATANI ,  Ryoji ISHIKAWA ,  Kenta SUTO

IPC分类号： G06F17/50

CPC分类号： G06F17/5072 ,  G06F17/5031 ,  G06F2217/84

摘要： To considerably reduce the cell layout change after timing optimization to reduce the term of layout design by estimating timing and an area after the timing optimization.During the period of initial layout processing using a net list, a timing constraint, a floor plan, a layout library, a timing library, etc., a library for estimating timing/area for estimating the timing and area after the timing optimization is created in advance and whether the timing constraint can be met is estimated. A cell in a path that hardly meets the timing constraint is placed in proximity and conversely, a cell that easily meets the timing constraint is placed at a distance. At this time, an area increase is also estimated so that wiring congestion does not occur.

摘要翻译： 为了大大减少定时优化后的单元布局变化，通过估计定时和定时优化后的面积来减少布局设计的期限。 在使用网表，定时约束，平面图，布局库，定时库等的初始布局处理期间，创建用于估计定时优化之后的定时和区域的定时/区域的库 估计是否可以满足时序约束。 几乎不能满足时序约束的路径中的单元被置于接近的位置，相反地，容易满足定时约束的单元被放置在一定距离处。 此时，还估计区域增加，使得不发生布线拥塞。