Jointly optimizing signal equalization and bit detection in a read channel

    公开(公告)号:US09768988B1

    公开(公告)日:2017-09-19

    申请号:US13722578

    申请日:2012-12-20

    CPC classification number: H04L25/03968 H04L25/03133 H04L25/03254

    Abstract: An apparatus and associated methodology providing read channel circuitry having a signal equalizer that sends an equalized signal to a bit detector. The read channel circuitry is capable of sampling values of the equalized signal to identify a bit transition from among a predefined plurality of different bit transitions. The apparatus may have channel optimization (CO) logic that, based on the input signal and the sampling of the equalized signal, defines first values for a programmable parameter of the bit detector that substantially maximizes vector separations among vectors of waveform target samples corresponding to the predefined plurality of different bit transitions, while the CO logic also defines second values for a programmable parameter of the equalizer that substantially minimizes the mean squared separation of the equalized signal segment for each bit transition from the waveform target corresponding to that bit transition.

    Servo gray code check bits
    2.
    发明授权
    Servo gray code check bits 有权
    伺服灰色码检查位

    公开(公告)号:US09178531B1

    公开(公告)日:2015-11-03

    申请号:US13869191

    申请日:2013-04-24

    CPC classification number: H03M13/05 H03M7/16 H03M13/09

    Abstract: The disclosure is related to systems and methods for achieving improved servo Gray code error detection and correction. A device may include a circuit configured to read servo data that is encoded using a Gray code encoding scheme to produce servo Gray code, read one or more Check bits associated with the servo Gray code, determine whether a read or write head is positioned over a target data track based on the servo Gray code and the one or more Check bits, and execute a read or write operation when the read or write head is positioned over the target data track.

    Abstract translation: 本公开涉及用于实现改进的伺服格雷码错误检测和校正的系统和方法。 设备可以包括被配置为读取使用格雷码编码方案编码以产生伺服格雷码的伺服数据的电路,读取与伺服格雷码相关联的一个或多个检查位,确定读或写头是否位于 基于伺服格雷码和一个或多个检查位的目标数据轨迹,并且当读或写头位于目标数据轨道上方时执行读或写操作。

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