公开(公告)号：US5870041A

公开(公告)日：1999-02-09

申请号：US773481

申请日：1996-12-23

申请人： Seong-Ho Lee ,  Euro Joe

发明人： Seong-Ho Lee ,  Euro Joe

IPC分类号： H03M1/06 ,  H03M1/10 ,  H03M1/12 ,  H03M1/46

CPC分类号： H03M1/1042

摘要： A digitally compensated analog-to-digital converter (ADC) provides improved linearity by generating calibration values having higher resolution than the output signal generated during a normal conversion. During a calibration value generation operation, the converter performs a normal conversion, then performs an additional conversion, thereby generating a high resolution calibration value which is then rounded and stored in a memory device. The converter includes a flash ADC which converts an analog input signal received through a multiplexer and sample-hold amplifier to a digital signal. The flash ADC provides control signals to a multibit digital-to-analog converter which generates the analog reconfiguration signal during multi-stage conversions. A digital correction circuit receives the digital signals from several multi-stage conversion and generates a corrected signal. A digital calibration circuit stores the rounded calibration values during a calibration value generation operation and generates a digital calibration signal which is added to the corrected signal during a normal operation to generate a digitally compensated signal.

摘要翻译： 数字补偿模数转换器（ADC）通过产生具有比在正常转换期间产生的输出信号更高的分辨率的校准值来提供改进的线性度。 在校准值生成操作期间，转换器执行正常转换，然后执行附加转换，从而生成高分辨率校准值，然后将其舍入并存储在存储器件中。 转换器包括闪存ADC，其将通过多路复用器和采样保持放大器接收的模拟输入信号转换为数字信号。 闪存ADC向多位数模转换器提供控制信号，在多级转换期间产生模拟重配置信号。 数字校正电路从多级转换接收数字信号并产生校正信号。 数字校准电路在校准值生成操作期间存储舍入的校准值，并且在正常操作期间产生加到校正信号的数字校准信号以产生数字补偿信号。