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公开(公告)号:US10914966B2
公开(公告)日:2021-02-09
申请号:US15533012
申请日:2017-04-25
Inventor: Yanhong Meng , Zhixiong Jiang
IPC: G02B30/27 , G02F1/1337 , G02F1/1335 , G02F1/13 , G02B30/25
Abstract: The disclosure discloses a manufacturing method of a liquid crystal display grating. The method includes preparing a substrate, depositing a transparent film layer on the substrate, patterning the transparent film layer for producing a plurality of containing grooves, depositing a liquid crystal alignment film in the containing grooves, injecting liquid crystal molecules in the containing grooves, aligning and packaging the liquid crystal molecules. The disclosure can achieve 3D display by the method above.
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公开(公告)号:US10186678B2
公开(公告)日:2019-01-22
申请号:US15504024
申请日:2017-01-17
Inventor: Zhixiong Jiang
Abstract: The present disclosure discloses an OLED component, comprising: a substrate, a bottom electrode arranged on the substrate, a top electrode opposite to the bottom electrode, and the top electrode spaced apart from the bottom electrode; an organic electroluminescence element arranged between the bottom electrode and the top electrode; at least one buffer element disposed between the top electrode and the organic electroluminescence element, and/or between the bottom electrode and the organic electroluminescence element, wherein the buffer element is configured to enhance carrier balance and, electrons transport performance and holes transport performance. The present disclosure enhances the luminous efficiency by the way of disposing the buffer element which is configured to enhance carrier balance, a electrons transport performance and holes transport performance between the top electrode and the organic electroluminescence element, and/or between the bottom electrode and the organic electroluminescence element.
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公开(公告)号:US10050626B2
公开(公告)日:2018-08-14
申请号:US15308586
申请日:2016-08-31
Inventor: Zhixiong Jiang
IPC: H03K19/0948 , H03K19/20
CPC classification number: H03K19/0948 , H03K19/20
Abstract: Disclosed is a CMOS inverter, including a first selector, a second selector, and a first transistor, a second transistor, a third transistor and a fourth transistor, which respectively are coupled to the input end of the CMOS inverter through the gates, and all the first transistor, the second transistor, the third transistor and the fourth transistor are coupled to the output end of the CMOS inverter, and sources of the first, the third transistors are respectively and correspondingly coupled to a first output end and a second output end of the first selector, and sources of the second, the fourth transistors are respectively and correspondingly coupled to a first output end and a second output end of the second selector; both the first selector and the second selector receive a first control signal and a second control signal, and both are coupled to the input end.
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