公开(公告)号：US08710555B2

公开(公告)日：2014-04-29

申请号：US13417744

申请日：2012-03-12

申请人： Shigenobu Maeda ,  Jeong Hwan Yang ,  Junga Choi

发明人： Shigenobu Maeda ,  Jeong Hwan Yang ,  Junga Choi

IPC分类号： H01L29/06

CPC分类号： H01L29/7854 ,  H01L29/045 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7855

摘要： In a semiconductor capable of reducing NBTI and a method for manufacturing the same, a multi-gate transistor includes an active region, gate dielectric, channels in the active region, and gate electrodes, and is formed on a semiconductor wafer. The active region has a top and side surfaces, and is oriented in a first direction. The gate dielectric is formed on the top and side surfaces of the active region. The channels are formed in the top and side surfaces of the active region. The gate electrodes are formed on the gate dielectric corresponding to the channels and aligned perpendicular to the active region such that current flows in the first direction. In one aspect of the invention, an SOI layer having a second orientation indicator in a second direction is formed on a supporting substrate having a first orientation indicator in a first direction.

摘要翻译： 在能够减少NBTI的半导体及其制造方法中，多栅极晶体管包括有源区，栅极电介质，有源区中的沟道和栅电极，并形成在半导体晶片上。 有源区具有顶表面和侧表面，并且在第一方向上定向。 栅电介质形成在有源区的顶表面和侧表面上。 通道形成在有源区域的顶表面和侧表面中。 栅极电极形成在对应于沟道的栅极电介质上并垂直于有源区域排列，使得电流在第一方向上流动。 在本发明的一个方面中，在具有第一方向的第一取向指示器的支撑基板上形成具有第二方向的第二取向指示器的SOI层。

公开(公告)号：US20080211022A1

公开(公告)日：2008-09-04

申请号：US12008232

申请日：2008-01-09

申请人： Shigenobu Maeda ,  Jeong Hwan Yang ,  Junga Choi

发明人： Shigenobu Maeda ,  Jeong Hwan Yang ,  Junga Choi

IPC分类号： H01L29/00 ,  H01L21/336

CPC分类号： H01L29/7854 ,  H01L29/045 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7855

摘要： In a semiconductor capable of reducing NBTI and a method for manufacturing the same, a multi-gate transistor includes an active region, gate dielectric, channels in the active region, and gate electrodes, and is formed on a semiconductor wafer. The active region has a top and side surfaces, and is oriented in a first direction. The gate dielectric is formed on the top and side surfaces of the active region. The channels are formed in the top and side surfaces of the active region. The gate electrodes are formed on the gate dielectric corresponding to the channels and aligned perpendicular to the active region such that current flows in the first direction. In one aspect of the invention, an SOI layer having a second orientation indicator in a second direction is formed on a supporting substrate having a first orientation indicator in a first direction. A multi-gate transistor is formed on the SOI layer. The first direction and the second direction are the same, or the first direction is at 45 degrees with respect to the second direction. In another aspect of the invention, the intersection of the top and side surfaces of the active region are curved, further reducing NBTI. In another aspect of the invention, a multi-gate transistor is formed on a shallow trench isolation region of a bulk wafer.

摘要翻译： 在能够减少NBTI的半导体及其制造方法中，多栅极晶体管包括有源区，栅极电介质，有源区中的沟道和栅电极，并形成在半导体晶片上。 有源区具有顶表面和侧表面，并且在第一方向上定向。 栅电介质形成在有源区的顶表面和侧表面上。 通道形成在有源区域的顶表面和侧表面中。 栅极电极形成在对应于沟道的栅极电介质上并垂直于有源区域排列，使得电流在第一方向上流动。 在本发明的一个方面中，在具有第一方向的第一取向指示器的支撑基板上形成具有第二方向的第二取向指示器的SOI层。 在SOI层上形成多栅极晶体管。 第一方向和第二方向相同，或者第一方向相对于第二方向成45度。 在本发明的另一方面，活性区域的顶表面和侧表面的交叉是弯曲的，进一步减少了NBTI。 在本发明的另一方面，多栅晶体管形成在体晶片的浅沟槽隔离区上。

公开(公告)号：US09123811B2

公开(公告)日：2015-09-01

申请号：US13417706

申请日：2012-03-12

申请人： Shigenobu Maeda ,  Jeong Hwan Yang ,  Junga Choi

发明人： Shigenobu Maeda ,  Jeong Hwan Yang ,  Junga Choi

IPC分类号： H01L29/786 ,  H01L29/04 ,  H01L29/78 ,  H01L29/66

CPC分类号： H01L29/7854 ,  H01L29/045 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7855

摘要： In a semiconductor capable of reducing NBTI and a method for manufacturing the same, a multi-gate transistor includes an active region, gate dielectric, channels in the active region, and gate electrodes, and is formed on a semiconductor wafer. The active region has a top and side surfaces, and is oriented in a first direction. The gate dielectric is formed on the top and side surfaces of the active region. The channels are formed in the top and side surfaces of the active region. The gate electrodes are formed on the gate dielectric corresponding to the channels and aligned perpendicular to the active region such that current flows in the first direction. In one aspect of the invention, an SOI layer having a second orientation indicator in a second direction is formed on a supporting substrate having a first orientation indicator in a first direction.

摘要翻译： 在能够减少NBTI的半导体及其制造方法中，多栅极晶体管包括有源区，栅极电介质，有源区中的沟道和栅电极，并形成在半导体晶片上。 有源区具有顶表面和侧表面，并且在第一方向上定向。 栅电介质形成在有源区的顶表面和侧表面上。 通道形成在有源区域的顶表面和侧表面中。 栅极电极形成在对应于沟道的栅极电介质上并垂直于有源区域排列，使得电流在第一方向上流动。 在本发明的一个方面中，在具有第一方向的第一取向指示器的支撑基板上形成具有第二方向的第二取向指示器的SOI层。

公开(公告)号：US20120168827A1

公开(公告)日：2012-07-05

申请号：US13417706

申请日：2012-03-12

申请人： Shigenobu Maeda ,  Jeong Hwan Yang ,  Junga Choi

发明人： Shigenobu Maeda ,  Jeong Hwan Yang ,  Junga Choi

IPC分类号： H01L29/786 ,  H01L29/04

CPC分类号： H01L29/7854 ,  H01L29/045 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7855

摘要： In a semiconductor capable of reducing NBTI and a method for manufacturing the same, a multi-gate transistor includes an active region, gate dielectric, channels in the active region, and gate electrodes, and is formed on a semiconductor wafer. The active region has a top and side surfaces, and is oriented in a first direction. The gate dielectric is formed on the top and side surfaces of the active region. The channels are formed in the top and side surfaces of the active region. The gate electrodes are formed on the gate dielectric corresponding to the channels and aligned perpendicular to the active region such that current flows in the first direction. In one aspect of the invention, an SOI layer having a second orientation indicator in a second direction is formed on a supporting substrate having a first orientation indicator in a first direction.

摘要翻译： 在能够减少NBTI的半导体及其制造方法中，多栅极晶体管包括有源区，栅极电介质，有源区中的沟道和栅电极，并形成在半导体晶片上。 有源区具有顶表面和侧表面，并且在第一方向上定向。 栅电介质形成在有源区的顶表面和侧表面上。 通道形成在有源区域的顶表面和侧表面中。 栅极电极形成在对应于沟道的栅极电介质上并垂直于有源区域排列，使得电流在第一方向上流动。 在本发明的一个方面中，在具有第一方向的第一取向指示器的支撑基板上形成具有第二方向的第二取向指示器的SOI层。

公开(公告)号：US07339213B2

公开(公告)日：2008-03-04

申请号：US11024616

申请日：2004-12-29

申请人： Shigenobu Maeda ,  Jeong Hwan Yang ,  Junga Choi

发明人： Shigenobu Maeda ,  Jeong Hwan Yang ,  Junga Choi

IPC分类号： H01L29/06

CPC分类号： H01L29/7854 ,  H01L29/045 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7855

摘要： In a semiconductor capable of reducing NBTI and a method for manufacturing the same, a multi-gate transistor includes an active region, gate dielectric, channels in the active region, and gate electrodes, and is formed on a semiconductor wafer. The active region has a top and side surfaces, and is oriented in a first direction. The gate dielectric is formed on the top and side surfaces of the active region. The channels are formed in the top and side surfaces of the active region. The gate electrodes are formed on the gate dielectric corresponding to the channels and aligned perpendicular to the active region such that current flows in the first direction. In one aspect of the invention, an SOI layer having a second orientation indicator in a second direction is formed on a supporting substrate having a first orientation indicator in a first direction. A multi-gate transistor is formed on the SOI layer. The first direction and the second direction are the same, or the first direction is at 45 degrees with respect to the second direction. In another aspect of the invention, the intersection of the top and side surfaces of the active region are curved, further reducing NBTI. In another aspect of the invention, a multi-gate transistor is formed on a shallow trench isolation region of a bulk wafer.

公开(公告)号：US20120168828A1

公开(公告)日：2012-07-05

申请号：US13417744

申请日：2012-03-12

申请人： Shigenobu Maeda ,  Jeong Hwan Yang ,  Junga Choi

发明人： Shigenobu Maeda ,  Jeong Hwan Yang ,  Junga Choi

IPC分类号： H01L29/78

CPC分类号： H01L29/7854 ,  H01L29/045 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7855

摘要： In a semiconductor capable of reducing NBTI and a method for manufacturing the same, a multi-gate transistor includes an active region, gate dielectric, channels in the active region, and gate electrodes, and is formed on a semiconductor wafer. The active region has a top and side surfaces, and is oriented in a first direction. The gate dielectric is formed on the top and side surfaces of the active region. The channels are formed in the top and side surfaces of the active region. The gate electrodes are formed on the gate dielectric corresponding to the channels and aligned perpendicular to the active region such that current flows in the first direction. In one aspect of the invention, an SOI layer having a second orientation indicator in a second direction is formed on a supporting substrate having a first orientation indicator in a first direction.

公开(公告)号：US08159006B2

公开(公告)日：2012-04-17

申请号：US12008232

申请日：2008-01-09

申请人： Shigenobu Maeda ,  Jeong-Hwan Yang ,  Junga Choi

发明人： Shigenobu Maeda ,  Jeong-Hwan Yang ,  Junga Choi

IPC分类号： H01L29/06

CPC分类号： H01L29/7854 ,  H01L29/045 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7855

摘要： In a semiconductor capable of reducing NBTI and a method for manufacturing the same, a multi-gate transistor includes an active region, gate dielectric, channels in the active region, and gate electrodes, and is formed on a semiconductor wafer. The active region has a top and side surfaces, and is oriented in a first direction. The gate dielectric is formed on the top and side surfaces of the active region. The channels are formed in the top and side surfaces of the active region. The gate electrodes are formed on the gate dielectric corresponding to the channels and aligned perpendicular to the active region such that current flows in the first direction. In one aspect of the invention, an SOI layer having a second orientation indicator in a second direction is formed on a supporting substrate having a first orientation indicator in a first direction. A multi-gate transistor is formed on the SOI layer. The first direction and the second direction are the same, or the first direction is at 45 degrees with respect to the second direction. In another aspect of the invention, the intersection of the top and side surfaces of the active region are curved, further reducing NBTI. In another aspect of the invention, a multi-gate transistor is formed on a shallow trench isolation region of a bulk wafer.

摘要翻译： 在能够减少NBTI的半导体及其制造方法中，多栅极晶体管包括有源区，栅极电介质，有源区中的沟道和栅电极，并形成在半导体晶片上。 有源区具有顶表面和侧表面，并且在第一方向上定向。 栅电介质形成在有源区的顶表面和侧表面上。 通道形成在有源区域的顶表面和侧表面中。 栅极电极形成在对应于沟道的栅极电介质上并垂直于有源区域排列，使得电流在第一方向上流动。 在本发明的一个方面中，在具有第一方向的第一取向指示器的支撑基板上形成具有第二方向的第二取向指示器的SOI层。 在SOI层上形成多栅极晶体管。 第一方向和第二方向相同，或者第一方向相对于第二方向成45度。 在本发明的另一方面，活性区域的顶表面和侧表面的交叉是弯曲的，进一步减少了NBTI。 在本发明的另一方面，多栅晶体管形成在体晶片的浅沟槽隔离区上。

公开(公告)号：US20050184283A1

公开(公告)日：2005-08-25

申请号：US11024616

申请日：2004-12-29

申请人： Shigenobu Maeda ,  Jeong Hwan Yang ,  Junga Choi

发明人： Shigenobu Maeda ,  Jeong Hwan Yang ,  Junga Choi

IPC分类号： H01L21/336 ,  H01L29/04 ,  H01L29/10 ,  H01L29/786 ,  H01L31/036 ,  H01L47/00

CPC分类号： H01L29/7854 ,  H01L29/045 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7855

摘要： In a semiconductor capable of reducing NBTI and a method for manufacturing the same, a multi-gate transistor includes an active region, gate dielectric, channels in the active region, and gate electrodes, and is formed on a semiconductor wafer. The active region has a top and side surfaces, and is oriented in a first direction. The gate dielectric is formed on the top and side surfaces of the active region. The channels are formed in the top and side surfaces of the active region. The gate electrodes are formed on the gate dielectric corresponding to the channels and aligned perpendicular to the active region such that current flows in the first direction. In one aspect of the invention, an SOI layer having a second orientation indicator in a second direction is formed on a supporting substrate having a first orientation indicator in a first direction. A multi-gate transistor is formed on the SOI layer. The first direction and the second direction are the same, or the first direction is at 45 degrees with respect to the second direction. In another aspect of the invention, the intersection of the top and side surfaces of the active region are curved, further reducing NBTI. In another aspect of the invention, a multi-gate transistor is formed on a shallow trench isolation region of a bulk wafer.

摘要翻译： 在能够减少NBTI的半导体及其制造方法中，多栅极晶体管包括有源区，栅极电介质，有源区中的沟道和栅电极，并形成在半导体晶片上。 有源区具有顶表面和侧表面，并且在第一方向上定向。 栅电介质形成在有源区的顶表面和侧表面上。 通道形成在有源区域的顶表面和侧表面中。 栅极电极形成在对应于沟道的栅极电介质上并垂直于有源区域排列，使得电流在第一方向上流动。 在本发明的一个方面中，在具有第一方向的第一取向指示器的支撑基板上形成具有第二方向的第二取向指示器的SOI层。 在SOI层上形成多栅极晶体管。 第一方向和第二方向相同，或者第一方向相对于第二方向成45度。 在本发明的另一方面，活性区域的顶表面和侧表面的交叉是弯曲的，进一步减少了NBTI。 在本发明的另一方面，多栅晶体管形成在体晶片的浅沟槽隔离区上。