公开(公告)号：US06789055B1

公开(公告)日：2004-09-07

申请号：US09706829

申请日：2000-11-07

申请人： Shigeru Kuriyama ,  Masahiko Oomura ,  Chie Hiramine ,  Hiromi Fujita ,  Masanori Kurimoto ,  Takeshi Shibagaki

发明人： Shigeru Kuriyama ,  Masahiko Oomura ,  Chie Hiramine ,  Hiromi Fujita ,  Masanori Kurimoto ,  Takeshi Shibagaki

IPC分类号： G06F1750

CPC分类号： G06F17/5031

摘要： The outputting of an output pulse produced in response to the inputting of a data pulse and a clock pulse to a D type flip-flop circuit is repeatedly simulated in a simulation process to extract a pulse time difference between the data pulse and the clock pulse as a timing verification checking value in a checking value extracting process on condition that the level of the output pulse becomes higher than a reference voltage until a simulation completion time and the pulse time difference is within a prescribed range. After the first simulation, an optimum simulation completion time, at which the levels of the data pulse, the clock pulse and the output pulse are respectively set to a constant high value, is determined to be place the optimum simulation completion time between a simulation start time and the simulation completion time, and the level of the output pulse is checked at the optimum simulation completion time in simulations following the first simulation. Therefore, a pulse time difference sufficiently made small can be rapidly and reliably extracted as a timing verification checking value.

摘要翻译： 在模拟处理中反复模拟响应于向D型触发器电路输入数据脉冲和时钟脉冲而产生的输出脉冲的输出，以提取数据脉冲和时钟脉冲之间的脉冲时间差，作为 在输出脉冲的电平变得比直到模拟完成时间为止的参考电压和脉冲时间差在规定范围内的条件下，在检查值提取处理中的定时验证检查值。 在第一次模拟之后，将数据脉冲，时钟脉冲和输出脉冲的电平分别设置为恒定的高值的最佳模拟完成时间被确定为在模拟开始之间放置最佳模拟完成时间 时间和模拟完成时间，并且在第一次模拟之后的模拟中，在最佳模拟完成时间检查输出脉冲的电平。 因此，可以迅速且可靠地提取足够小的脉冲时间差作为定时验证检查值。