公开(公告)号：US5751618A

公开(公告)日：1998-05-12

申请号：US391871

申请日：1995-02-22

申请人： Shigeshi Abiko ,  Shintaro Mizushima ,  Marc Couvrat

发明人： Shigeshi Abiko ,  Shintaro Mizushima ,  Marc Couvrat

IPC分类号： G06F7/50 ,  G06F7/506 ,  G06F7/507 ,  G06F7/53 ,  G06F7/533 ,  G06F7/57 ,  G06F17/10 ,  G06F7/38

CPC分类号： G06F7/57

摘要： An arithmetic circuit is provided in which the circuit scale can be reduced and the circuit delay can be shortened. The upper 24 bits and lower 16 bits of the 40 bit data A and B, that is input into the arithmetic circuit 100, are calculated in the first arithmetic circuit 110 and the second arithmetic circuit 120, respectively. The carry transmission control circuit 130 transmits the carry between the arithmetic circuit 120 and the arithmetic circuit 110 when the arithmetic circuit dividing signal p does not divide the arithmetic circuit, and the command control circuit 140 outputs an identical command to each of the arithmetic circuits. As a result, this circuit becomes an arithmetic circuit of 40 bits. The carry transmission control circuit 130 stops the transmission of the carry between the arithmetic circuit 120 and the arithmetic circuit 110 when the signal p divides the arithmetic circuit, and the command control circuit 140 outputs each of the independent commands to each of the arithmetic circuits. As a result, this circuit becomes a parallel arithmetic circuit of 24 bits and 16 bits.

摘要翻译： 提供了一种算术电路，其中可以减小电路规模，并且可以缩短电路延迟。 分别在第一运算电路110和第二运算电路120中计算输入到运算电路100的40位数据A和B的高24位和低16位。 当运算电路分配信号p不分配算术电路时，进位传送控制电路130传送运算电路120和运算电路110之间的进位，并且命令控制电路140向每个运算电路输出相同的命令。 结果，该电路成为40位的运算电路。 当信号p分割运算电路时，进位传输控制电路130停止运算电路120和运算电路110之间的进位的传输，并且命令控制电路140将每个独立命令输出到每个运算电路。 结果，该电路成为24位和16位的并行运算电路。