公开(公告)号：US3940567A

公开(公告)日：1976-02-24

申请号：US528240

申请日：1974-11-29

申请人： Shinichi Iki ,  Hideaki Kosugi

发明人： Shinichi Iki ,  Hideaki Kosugi

IPC分类号： G08C15/12 ,  H04J3/12 ,  H04J7/00

CPC分类号： G08C15/12 ,  H04J3/12 ,  H04J7/00

摘要： Control pulses of highest positive level, clock pulses of negative middle level and reset pulses of lowest negative level are transmitted through one or more transmission lines. Separation of those pulses in the receiver is performed by means of simple rectifiers connected to the transmission lines. In both transmitter and receiver, binary counters and decimal decoders are utilized for repeatedly producing channel pulse sequences.

摘要翻译： 最高正电平的控制脉冲，负中等电平的时钟脉冲和最低负电平的复位脉冲通过一条或多条传输线传输。 通过连接到传输线的简单整流器来执行接收机中这些脉冲的分离。 在发射机和接收机中，二进制计数器和十进制解码器都用于重复产生通道脉冲序列。