公开(公告)号：US20170093388A1

公开(公告)日：2017-03-30

申请号：US14871734

申请日：2015-09-30

Applicant: Silicon Laboratories Inc.

Inventor： CHAO YANG ,  Matthew Powell

IPC: H03K17/082

CPC classification number: H03K19/0185

Abstract: An apparatus includes an integrated circuit, which includes a processor core, a plurality of input/output (I/O) circuits, and a plurality of over voltage tolerant (OVT) circuits. Each I/O circuit is associated with an I/O pad and is associated with an OVT circuit of the plurality of OVT circuits. At least one of the OVT circuits includes a passive circuit, which is adapted to receive a pad voltage from the associated I/O pad; receive a supply voltage of the associated I/O circuit; and based on a relationship of the received pad voltage relative to the received supply voltage, selectively couple a gate of a transistor of the associated I/O circuit to the pad voltage to inhibit a leakage current.