公开(公告)号：US11200930B1

公开(公告)日：2021-12-14

申请号：US17109398

申请日：2020-12-02

Applicant: Silicon Laboratories Inc.

Inventor： Harikrishnan Prabha Valsala ,  Hong Lee Koo ,  Shantonu Bhadury

IPC: G11C7/22 ,  G11C7/04 ,  G11C7/10

Abstract: A memory system including a memory device, cache controller circuitry, and timing circuitry. The memory device has a read enable input for receiving a read enable indication for requesting stored data, and has a minimum delay specification between consecutive read enable indications. The cache controller circuitry provides a read indication during a prefetch mode to read data from a next linear address from the memory device, provides a reading indication while data is being read, and provides a miss indication when a next processor address is not the next linear address. The timing circuitry includes synchronization circuitry receiving the read indication and a clock signal and provides a preliminary read enable indication, read enable circuitry receiving a mask indication and the preliminary read enable indication and providing the read enable indication, and mask circuitry that provides the mask indication when the reading indication and the miss indication are both provided.