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公开(公告)号:US10289840B2
公开(公告)日:2019-05-14
申请号:US15612841
申请日:2017-06-02
Applicant: Silicon Laboratories Inc.
Inventor: Javier Elenes , Sebastian Ahmed , Lars Lydersen
Abstract: An integrated circuit includes a tamper sensor that has plurality of state circuits. Each of the plurality of state circuits has a respective output that provides a respective logic state. When operating properly, the respective logic state is toggled in response to a clock signal. The respective logic state fails to toggle in response to a respective fault injection. The tamper sensor has an output that provides a fault signal in response to a difference in the respective logic state of the plurality of state circuits. Additionally, the integrated circuit includes a protected circuit, as well as a tamper response circuit. The tamper response circuit is connected to the tamper sensor and to the protected circuit. The tamper response circuit executes a protection operation to secure the protected circuit in response to the fault signal.
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公开(公告)号:US20180349600A1
公开(公告)日:2018-12-06
申请号:US15612841
申请日:2017-06-02
Applicant: Silicon Laboratories Inc.
Inventor: Javier Elenes , Sebastian Ahmed , Lars Lydersen
CPC classification number: G06F21/554 , G06F21/556 , G06F21/725
Abstract: An integrated circuit includes a tamper sensor that has plurality of state circuits. Each of the plurality of state circuits has a respective output that provides a respective logic state. When operating properly, the respective logic state is toggled in response to a clock signal. The respective logic state fails to toggle in response to a respective fault injection. The tamper sensor has an output that provides a fault signal in response to a difference in the respective logic state of the plurality of state circuits. Additionally, the integrated circuit includes a protected circuit, as well as a tamper response circuit. The tamper response circuit is connected to the tamper sensor and to the protected circuit. The tamper response circuit executes a protection operation to secure the protected circuit in response to the fault signal.
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