公开(公告)号：US09800281B2

公开(公告)日：2017-10-24

申请号：US15470989

申请日：2017-03-28

Applicant: Silicon Laboratories Inc.

Inventor： Abdulkerim L. Coban ,  Alessandro Piovaccari ,  Ramin K. Poorfard ,  James T. Kao

IPC: H04B1/06 ,  H04B1/16 ,  H03G3/30

CPC classification number: H04B1/16 ,  H03G3/3068

Abstract: A signal processor for a radio frequency (RF) receiver includes a signal processing path having first and second programmable gain amplifiers and first and second offset correction circuits. The first offset correction circuit receives a first digital offset correction word and corrects a first offset of the first programmable gain amplifier by adding a first value corresponding to the first digital offset correction word to an input of the first programmable gain amplifier. The second offset correction circuit receives a second digital offset correction word and corrects a second offset of the second programmable gain amplifier by adding a first value corresponding to the second digital offset correction word to an input of the second programmable gain amplifier. A controller measures offsets of the first and second programmable gain amplifiers during a calibration, and provides the first and second offset correction words in response to the offsets.

公开(公告)号：US20170201282A1

公开(公告)日：2017-07-13

申请号：US15470989

申请日：2017-03-28

Applicant: Silicon Laboratories Inc.

Inventor： Abdulkerim L. Coban ,  Alessandro Piovaccari ,  Ramin K. Poorfard ,  James T. Kao

IPC: H04B1/16 ,  H03G3/30

CPC classification number: H04B1/16 ,  H03G3/3068

Abstract: A signal processor for a radio frequency (RF) receiver includes a signal processing path having first and second programmable gain amplifiers and first and second offset correction circuits. The first offset correction circuit receives a first digital offset correction word and corrects a first offset of the first programmable gain amplifier by adding a first value corresponding to the first digital offset correction word to an input of the first programmable gain amplifier. The second offset correction circuit receives a second digital offset correction word and corrects a second offset of the second programmable gain amplifier by adding a first value corresponding to the second digital offset correction word to an input of the second programmable gain amplifier. A controller measures offsets of the first and second programmable gain amplifiers during a calibration, and provides the first and second offset correction words in response to the offsets.