Interface To Provide Selectable Time Domain Or Frequency Domain Information To Downstream Circuitry

    公开(公告)号:US20210036905A1

    公开(公告)日:2021-02-04

    申请号:US16527571

    申请日:2019-07-31

    Abstract: In one embodiment, an apparatus includes first and second tuners to receive and process a radio frequency (RF) signal and output a first and second plurality of frequency domain sub-carriers. The apparatus may further include a combiner circuit to combine a first plurality of demodulated frequency domain sub-carriers and a second plurality of demodulated frequency domain sub-carriers into a plurality of combined frequency domain sub-carriers, and an output circuit coupled to the combiner circuit. In a first mode, the output circuit is to embed a format indicator with each of the plurality of combined frequency domain sub-carriers to indicate a frequency domain format, and to output the plurality of combined frequency domain sub-carriers with the embedded format indicator to a downstream processing circuit for channel decoding.

    Interface to provide selectable time domain or frequency domain information to downstream circuitry

    公开(公告)号:US10911289B1

    公开(公告)日:2021-02-02

    申请号:US16527571

    申请日:2019-07-31

    Abstract: In one embodiment, an apparatus includes first and second tuners to receive and process a radio frequency (RF) signal and output a first and second plurality of frequency domain sub-carriers. The apparatus may further include a combiner circuit to combine a first plurality of demodulated frequency domain sub-carriers and a second plurality of demodulated frequency domain sub-carriers into a plurality of combined frequency domain sub-carriers, and an output circuit coupled to the combiner circuit. In a first mode, the output circuit is to embed a format indicator with each of the plurality of combined frequency domain sub-carriers to indicate a frequency domain format, and to output the plurality of combined frequency domain sub-carriers with the embedded format indicator to a downstream processing circuit for channel decoding.

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