公开(公告)号：US11630601B2

公开(公告)日：2023-04-18

申请号：US17515570

申请日：2021-11-01

Applicant: Silicon Motion, Inc.

Inventor： Cheng Yi ,  Kaihong Wang ,  Sheng-I Hsu ,  I-Ling Tseng

IPC: G06F3/06

Abstract: A method and apparatus for performing access control of a memory device with aid of a multi-phase memory-mapped queue are provided. The method includes: receiving a first host command from a host device; and in response to the first host command, utilizing a processing circuit within the controller to send a first operation command to the NV memory through a control logic circuit of the controller, and trigger a first set of secondary processing circuits within the controller to operate and interact via the multi-phase memory-mapped queue, for accessing the first data for the host device, wherein the processing circuit and the first set of secondary processing circuits share the multi-phase memory-mapped queue, and use the multi-phase memory-mapped queue as multiple chained message queues associated with multiple phases, respectively, for performing message queuing for a chained processing architecture including the processing circuit and the first set of secondary processing circuits.

公开(公告)号：US20220283732A1

公开(公告)日：2022-09-08

申请号：US17515570

申请日：2021-11-01

Applicant: Silicon Motion, Inc.

Inventor： Cheng Yi ,  Kaihong Wang ,  Sheng-I Hsu ,  I-Ling Tseng

IPC: G06F3/06

Abstract: A method and apparatus for performing access control of a memory device with aid of a multi-phase memory-mapped queue are provided. The method includes: receiving a first host command from a host device; and in response to the first host command, utilizing a processing circuit within the controller to send a first operation command to the NV memory through a control logic circuit of the controller, and trigger a first set of secondary processing circuits within the controller to operate and interact via the multi-phase memory-mapped queue, for accessing the first data for the host device, wherein the processing circuit and the first set of secondary processing circuits share the multi-phase memory-mapped queue, and use the multi-phase memory-mapped queue as multiple chained message queues associated with multiple phases, respectively, for performing message queuing for a chained processing architecture including the processing circuit and the first set of secondary processing circuits.

公开(公告)号：US11816360B2

公开(公告)日：2023-11-14

申请号：US17706645

申请日：2022-03-29

Applicant: Silicon Motion, Inc.

Inventor： Kaihong Wang ,  Cheng Yi

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/064 ,  G06F3/0604 ,  G06F3/0613 ,  G06F3/0631 ,  G06F3/0653 ,  G06F3/0679

Abstract: A method for performing data access performance shaping of a memory device and associated apparatus are provided. The method may include: receiving a plurality of host commands from a host device, for performing data access on the NV memory according to the plurality of host commands; and monitoring the plurality of host commands to control respective performance metrics of a plurality of access control groups of the memory device with a dual-state leaky bucket (LB) model, wherein regarding any access control group, for example: determining at least one first performance metric according to at least one first command to be a first LB fill level of a dual-state LB; in response to the first LB fill level being below a state threshold, determining the dual-state LB to be in a first predetermined state, and configuring the dual-state LB to have a first predetermined drain rate, for dynamically adjusting performance quota.

公开(公告)号：US20230315337A1

公开(公告)日：2023-10-05

申请号：US17706645

申请日：2022-03-29

Applicant: Silicon Motion, Inc.

Inventor： Kaihong Wang ,  Cheng Yi

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/0653 ,  G06F3/0631 ,  G06F3/064 ,  G06F3/0613 ,  G06F3/0604 ,  G06F3/0679

Abstract: A method for performing data access performance shaping of a memory device and associated apparatus are provided. The method may include: receiving a plurality of host commands from a host device, for performing data access on the NV memory according to the plurality of host commands; and monitoring the plurality of host commands to control respective performance metrics of a plurality of access control groups of the memory device with a dual-state leaky bucket (LB) model, wherein regarding any access control group, for example: determining at least one first performance metric according to at least one first command to be a first LB fill level of a dual-state LB; in response to the first LB fill level being below a state threshold, determining the dual-state LB to be in a first predetermined state, and configuring the dual-state LB to have a first predetermined drain rate, for dynamically adjusting performance quota.